Abstract: Provided is a semiconductor integrated circuit device capable of, when data is written into a memory cell, fixing adjacent complimentary bit lines to a predetermined voltage, thereby reducing an effect of a write noise for a readout operation of the adjacent cells, making it possible to ensure stable operation. An address signal is inputted to a bit line short signal circuit and a column switch signal circuit, and the corresponding bit line short signal BRS0 or BRS1 and column switch signal CL01 or CL11 are selected. Complimentary bit lines /BL1, /BL2 or bit lines BL1 and BL2 in which a memory cell is not connected according to the bit line short signals BRS0 and BRS1 are selected altogether, these bit lines are fixed to a precharge voltage VPR, and a write noise is shielded. The column switch signal CL01 or CL11 makes conductive the corresponding column switches, and the selected bit line BL1, BL2, /BL1, or /BL2 is connected to a data bus DB or /DB.

Abstract: It is intended to provide a semiconductor integrated circuit device and adjustment method of the same semiconductor integrated circuit device, capable of adjusting an analog signal outputted from an incorporated analog signal generating section without outputting it outside as an analog value. An analog signal AOUT is outputted from an analog signal generating section 3 in which an adjustment signal AD is inputted. The analog signal AOUT is inputted to a judgment section 1, in which it is compared and judged with a predetermined value and then a judgment signal JG is outputted. The judgment signal JG acts on a predetermined signal storing section 4 as an internal signal and the adjustment signal AD is fetched into the predetermined signal storing section 4. Further, the judgment signal JG is outputted as digital signal through an external terminal T2 and an external tester device acquires the adjustment signal and stores the acquired adjustment signal in the predetermined signal storing section 4.

Abstract: A semiconductor device includes both a logic circuit and a macro circuit. The macro circuit includes a circuit that consumes direct current (DC). In order to conserve power and allow for testing, the consumption of DC by the current consumption circuit can be stopped with a stop signal, which stops the operation of the macro circuit. The macro circuit can be restarted or returned to normal operation mode without risk of error caused by the stopping of the macro circuit.

Abstract: The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

Abstract: There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation-frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value.

Abstract: A semiconductor integrated circuit that acquires an external signal precisely in a high speed operation. The semiconductor integrated circuit includes an internal circuit for acquiring an external signal in response to an address acquisition signal. A first holding circuit is connected to the internal circuit to hold the external signal for a predetermined period in response to a holding signal and provide the held external signal to the internal circuit. A control circuit is connected to the first holding circuit to generate the holding signal using the address acquisition signal.

Abstract: This invention provides a semiconductor memory device with a shift redundancy circuit which has a shortened redundancy operation. The semiconductor memory device of the present invention includes a plurality of shift switches and a changeover signal generating circuit connected to the shift switches. The changeover signal generating circuit may have a plurality of signal generating blocks including a first signal generating block for generating a first group of changeover signals and a second signal generating block for generating a second group of changeover signals.

Abstract: There is intended to provide a semiconductor integrated circuit device capable of lowering the power consumption during data-write operation, enhancing operation speed, and reducing noises for stable operation. In the semiconductor integrated circuit, an active signal ACT to be inputted to a sense amplifier signal circuit SC1 is latched by a command latch circuit and outputted to a terminal N11. The terminal N11 outputs a control signal EDC1 via a timing adjusting circuit. The control signal EDC1 works to output a sense amplifier activating signal LE via a timing adjusting circuit and output buffer circuit and at the same time, the control signal EDC1 is outputted to a column switch signal circuit CS1. From the Column switch signal circuit CS1, a pulse signal is outputted via input of a control signal ACL, a pulse output circuit, and a terminal N13. In a logical circuit, AND processing is conducted between the pulse signal and an inversion signal of the control signal EDC1.

Abstract: Provided is a semiconductor integrated circuit device capable of, when data is written into a memory cell, fixing adjacent complimentary bit lines to a predetermined voltage, thereby reducing an effect of a write noise for a readout operation of the adjacent cells, making it possible to ensure stable operation. An address signal is inputted to a bit line short signal circuit and a column switch signal circuit, and the corresponding bit line short signal BRS0 or BRS1 and column switch signal CL01 or CL11 are selected. Complimentary bit lines /BL1, /BL2 or bit lines BL1 and BL2 in which a memory cell is not connected according to the bit line short signals BRS0 and BRS1 are selected altogether, these bit lines are fixed to a precharge voltage VPR, and a write noise is shielded. The column switch signal CL01 or CL11 makes conductive the corresponding column switches, and the selected bit line BL1, BL2, /BL1, or /BL2 is connected to a data bus DB or /DB.

Abstract: There is intended to provide a semiconductor integrated circuit device capable of lowering the power consumption during data-write operation, enhancing operation speed, and reducing noises for stable operation. In the semiconductor integrated circuit, an active signal ACT to be inputted to a sense amplifier signal circuit SC1 is latched by a command latch circuit and outputted to a terminal N11. The terminal N11 outputs a control signal EDC1 via a timing adjusting circuit. The control signal EDC1 works to output a sense amplifier activating signal LE via a timing adjusting circuit and output buffer circuit and at the same time, the control signal EDC1 is outputted to a column switch signal circuit CS1. From the Column switch signal circuit CS1, a pulse signal is outputted via input of a control signal ACL, a pulse output circuit, and a terminal N13. In a logical circuit, AND processing is conducted between the pulse signal and an inversion signal of the control signal EDC1.

Abstract: A semiconductor integrated circuit that acquires an external signal precisely in a high speed operation. The semiconductor integrated circuit includes an internal circuit for acquiring an external signal in response to an address acquisition signal. A first holding circuit is connected to the internal circuit to hold the external signal for a predetermined period in response to a holding signal and provide the held external signal to the internal circuit. A control circuit is connected to the first holding circuit to generate the holding signal using the address acquisition signal.

Abstract: This invention provides a semiconductor memory device with a shift redundancy circuit which has a shortened redundancy operation. The semiconductor memory device of the present invention includes a plurality of shift switches and a changeover signal generating circuit connected to the shift switches. The changeover signal generating circuit may have a plurality of signal generating blocks including a first signal generating block for generating a first group of changeover signals and a second signal generating block for generating a second group of changeover signals.

Abstract: This invention provides a semiconductor memory device with a shift redundancy circuit which has a shortened redundancy operation. The semiconductor memory device of the present invention includes a plurality of shift switches and a changeover signal generating circuit connected to the shift switches. The changeover signal generating circuit may have a plurality of signal generating blocks including a first signal generating block for generating a first group of changeover signals and a second signal generating block for generating a second group of changeover signals.

Abstract: This invention provides a semiconductor memory device with a shift redundancy circuit which has a shortened redundancy operation. The semiconductor memory device of the present invention includes a plurality of shift switches and a changeover signal generating circuit connected to the shift switches. The changeover signal generating circuit may have a plurality of signal generating blocks including a first signal generating block for generating a first group of changeover signals and a second signal generating block for generating a second group of changeover signals.

Abstract: A system LSI circuit which includes multiple memory circuits and functional logic circuits includes a control circuit for controlling the voltage supplied to the memory circuits. The control circuit includes trimming circuits for adjusting the memory supply voltages to ensure that the supplied voltages are within predetermined tolerances. The control circuit services all of the memory circuits, such that redundant logic functions are consolidated and multiple pads are not required to measure the memory supply voltages.

Abstract: In a semiconductor memory device which is intended to lower the power consumption and raise the operation speed without increasing the circuit scale to meet trends toward the larger capacity, higher speed and, at the same time, the lower power voltage design, the precharge circuit Pre3 has its bit line shorting section formed of transistors TN1A and TN1B in series connection and its bit line voltage holding circuit formed of transistors TN2A and TN2B connected in series between the node of the transistors TN1A and TN1B and a precharge voltage VPR source, with the transistors TN1A and TN2A and the TN1B and TN2B being controlled by precharge signals BRS0 and BRS1, respectively. One of the precharge signals BRS0 and BRS1 is preset active since the former precharge operation cycle, the other precharge signal is activated to start the shorting operation of a bit line pair /BL-BL, and the preset precharge signal is deactivated to end the shorting operation.

Abstract: A semiconductor memory device, such as a SDRAM, includes input/output data line pairs, data bus line pairs, and a redundancy data bus line pair. The input/output data line pairs are connected to a corresponding one of the data bus line pairs and an adjacent one of the data bus line pairs via redundancy shift switches, with a last one of the input/output data line pairs being connected to a last one fo the data bus line pairs and the redundancy data bus line pair. Sense buffers and write amplifiers are connected between each of the data bus line pairs and the redundancy data line pair. The shift switches are located closer to the input/output data line pairs than the sense buffers and the write amplifiers so that data read from the memory cells is less effected by the on resistance and the parasitic capacitance of the switches. When the switches are located closer to the data bus lines than the sense buffers and the write amplifiers are, the switches effect the data signals of data read from the memory cells.

Abstract: A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

Abstract: A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

Abstract: A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on the floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.