Abstract: A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) on the germanium layer, and forming a gate electrode (e.g., titanium nitride 60) on the gate dielectric. The method may comprise forming source and drain regions 64 in the substrate on either side of the gate dielectric. The germanium layer, which is preferably epitaxially grown, generally prevents formation of a low dielectric constant layer between the gate dielectric and the semiconductor substrate. The disclosed structure comprises a germanium layer 52 disposed on a semiconductor substrate (e.g. silicon 20), a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) disposed on the germanium layer, and a gate electrode (e.g., titanium nitride 60) disposed on the gate dielectric.

Abstract: A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) on the germanium layer, and forming a gate electrode (e.g., titanium nitride 60) on the gate dielectric. The method may comprise forming source and drain regions 64 in the substrate on either side of the gate dielectric. The germanium layer, which is preferably epitaxially grown, generally prevents formation of a low dielectric constant layer between the gate dielectric and the semiconductor substrate. The disclosed structure comprises a germanium layer 52 disposed on a semiconductor substrate (e.g. silicon 20), a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) disposed on the germanium layer, and a gate electrode (e.g., titanium nitride 60) disposed on the gate dielectric.

Abstract: A silicon film is formed within a contact hole formed in a first insulating film on a semiconductor substrate in a manner that an upper portion of the contact hole remains, and a cobalt film is then deposited on the silicon film. Thereafter, a heat treatment is carried out so as to react the silicon film with the cobalt film, thereby forming a cobalt silicide layer in the surface portion of the silicon film. A barrier layer is formed on the cobalt silicide layer so as to completely fill the contact hole, and thus, a plug including the polysilicon film, the cobalt silicide layer and the barrier layer is formed. After a recess is formed in a second insulating film deposited on the first insulating film so as to expose the top surface of the plug, a capacitor bottom electrode, a capacitor dielectric film and a capacitor top electrode are successively formed in the recess.

Abstract: An isolation structure which protrudes above the semiconductor surface and sidewall spacers which smooth the topography over said isolation structure.

Abstract: An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contacts (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step.

Abstract: A method for forming integrated circuits having multiple gate oxide thicknesses. A high density plasma is used for selective plasma nitridation to reduce the effective gate dielectric thickness in selected areas only. In one embodiment, a pattern (12) is formed over a substrate (10) and a high density plasma nitridation is used to form a thin nitride or oxynitride layer (18) on the surface of the substrate (10) . The pattern (12) is removed and oxidation takes place. The nitride (or oxynitride) layer (18) retards oxidation (20b), whereas, in the areas (20a) where the nitride (or oxynitride) layer (18) is not present, oxidation is not retarded. In another embodiment, a thermal oxide is grown. A pattern is then placed that exposes areas where a thinner effective gate oxide is desired. The high density plasma nitridation is performed converting a portion of the gate oxide to nitride or oxynitride. The effective thickness of the combined gate dielectric is reduced.

Abstract: A dielectric capacitor is provided which has a reduced leakage current. The surface of a first electrode (38) of the capacitor is electropolished and a dielectric film (40) and a second electrode (37) are successively laminated on it. The convex parts pointed end (38a) existing on the surface of the first electrode is very finely polished uniformly by dissolving according to electropolishing, a spherical curved surface in which the radius of curvature has been enlarged is formed, and the surface of the first electrode is flattened. Therefore, concentration of electrolysis can be prevented during the operation at the interface of the first electrode and the dielectric film, and the leakage current can be reduced considerably.

Abstract: A semiconductor device with a multilayer wiring structure has an insulating substrate and first conductors formed on top of the insulating substrate with a groove between neighboring first conductors. An insulating film covers the first conductors as well as the grooves between the neighboring first conductors. A void serving to reduce electrostatic capacitance between the conductors is formed in the grooves. An interlayer insulating film is formed on top of the first conductors to prevent leakage current, and second conductors are formed on top of the interlayer insulating film.

Abstract: A resonant tunneling diode (400) made of a germanium quantum well (406) with silicon oxide tunneling barriers (404, 408). The silicon oxide tunneling barriers (404, 408) plus germanium quantum well (406) may be fabricated by oxygen segregation from germanium oxides to silicon oxides.

Abstract: A resonant tunneling diode (400) made of a germanium quantum well (406) with silicon oxide tunneling barriers (404, 408). The silicon oxide tunneling barriers (404, 408) plus germanium quantum well (406) may be fabricated by oxygen segregation from germanium oxides to silicon oxides.