Abstract: A multi-layer scavenging metal gate stack, and methods of manufacturing the same, are disclosed. In an example, a gate stack disposed over a semiconductor substrate includes an interfacial dielectric layer disposed over the semiconductor substrate, a high-k dielectric layer disposed over the interfacial dielectric layer, a first conductive layer disposed over the high-k dielectric layer, and a second conductive layer disposed over the first conductive layer. The first conductive layer includes a first metal layer disposed over the high-k dielectric layer, a second metal layer disposed over the first metal layer, and a third metal layer disposed over the second metal layer. The first metal layer includes a material that scavenges oxygen impurities from the interfacial dielectric layer, and the second metal layer includes a material that adsorbs oxygen impurities from the third metal layer and prevents oxygen impurities from diffusing into the first metal layer.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact.

Abstract: A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact.

Abstract: A gate stressor for a fin field effect transistor (FinFET) device is provided. The gate stressor includes a floor, a first stressor sidewall, and a second stressor sidewall. The floor is formed on a first portion of a gate layer. The gate layer is disposed above a shallow trench isolation (STI) region. The first stressor sidewall formed on a second portion of the gate layer. The second portion of the gate layer is disposed on sidewalls of a fin. The second stressor sidewall formed on the third portion of the gate layer. The third portion of the gate layer is disposed on sidewalls of a structure spaced apart from the fin. The first stressor side wall and the second stressor sidewall do not exceed a height of the fin.

Abstract: A multi-layer scavenging metal gate stack, and methods of manufacturing the same, are disclosed. In an example, a gate stack disposed over a semiconductor substrate includes an interfacial dielectric layer disposed over the semiconductor substrate, a high-k dielectric layer disposed over the interfacial dielectric layer, a first conductive layer disposed over the high-k dielectric layer, and a second conductive layer disposed over the first conductive layer. The first conductive layer includes a first metal layer disposed over the high-k dielectric layer, a second metal layer disposed over the first metal layer, and a third metal layer disposed over the second metal layer. The first metal layer includes a material that scavenges oxygen impurities from the interfacial dielectric layer, and the second metal layer includes a material that adsorbs oxygen impurities from the third metal layer and prevents oxygen impurities from diffusing into the first metal layer.

Abstract: The disclosure relates to integrated circuit fabrication and, more particularly, to a semiconductor device with a high-k gate dielectric layer. An exemplary structure for a semiconductor device comprises a substrate and a gate structure disposed over the substrate. The gate structure comprises a dielectric portion and an electrode portion that is disposed over the dielectric portion, and the dielectric portion comprises a carbon-doped high-k dielectric layer on the substrate and a carbon-free high-k dielectric layer adjacent to the electrode portion.

Abstract: A gate electrode is formed on a semiconductor substrate containing silicon, then source/drain regions are formed in regions of the semiconductor substrate located to both sides of the gate electrode, and then a nickel alloy silicide layer is formed on at least either the gate electrode or the source/drain regions. In the step of forming the nickel alloy silicide layer, a nickel alloy film and a nickel film are sequentially deposited on the semiconductor substrate and thereafter subjected to heat treatment.

Abstract: A method for manufacturing a dual work function device is disclosed. In one aspect, the process includes a first and second region in a substrate. The method includes forming a first transistor in the first region which has a first work function. Subsequently, a second transistor is formed in the second region having a different work function. The process of forming the first transistor includes providing a first gate dielectric stack having a first gate dielectric layer and a first gate dielectric capping layer on the first gate dielectric layer, performing a thermal treatment to modify the first gate dielectric stack, the modified first gate dielectric stack defining the first work function, providing a first metal gate electrode layer on the modified first gate dielectric stack, and patterning the first metal gate electrode layer and the modified first gate dielectric stack.

Abstract: A semiconductor device includes: a semiconductor substrate having an element formation region containing impurities of a first conductivity type; a gate electrode formed on the element formation region with a gate insulating film interposed therebetween; and a silicon alloy layer formed on a lateral side of the gate electrode in the element formation region, and containing impurities of a second conductivity type. A boundary layer containing impurities of the second conductivity type is formed between the silicon alloy layer and the element formation region.

Abstract: An electronic device includes an element group which generates a specific identification number and is composed of a plurality of elements. The specific identification number is set based on irregular deviation in electric characteristic of the elements which is caused due to a random failure in a manufacturing process.

Abstract: A gate electrode is formed on a silicon substrate, and then source/drain regions are formed at both sides of the gate electrode in the silicon substrate. Thereafter, an alloyed silicide layer is formed on the source/drain regions. The step of forming the alloyed silicide layer includes the step of depositing a first metal film, a nickel film and a second metal film in this order to form a multilayer metal film and the step of performing heat treatment after the formation of the multilayer metal film.

Abstract: After protective insulating films are formed on first to third active regions, the protective insulating films formed on the first and third active regions are removed. Subsequently, an insulating film to be a first gate insulating film is formed on each of the first and third active regions, and then, the protective insulating film formed on the second active region is removed. Next, an insulating film to be a second gate insulating film is formed on the second active region, and then, the insulating film to be the first gate insulating film formed on the third active region is removed. Finally, an insulating film to be a third gate insulating film is formed on the third active region.

Abstract: An electronic device includes an element group which generates a specific identification number and is composed of a plurality of elements. The specific identification number is set based on irregular deviation in electric characteristic of the elements which is caused due to a random failure in a manufacturing process.

Abstract: A semiconductor device includes a circuit formation region which is formed in a semiconductor substrate and includes a plurality of element formation regions surrounded by isolation regions, respectively. A stress effect relief region of a predetermined width is formed around the circuit formation region to relieve a stress effect of the isolation regions on the operation characteristics of elements formed in the element formation regions and a plurality of dummy features are formed in the stress effect relief region and other part of the circuit formation region than the element formation regions at predetermined distances, the dummy features having the same composition as the element formation regions and predetermined planar dimensions.

Abstract: Methods deposit a film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. Flows of first precursor deposition gases are provided to the substrate processing chamber. A first high-density plasma is formed from the flows of first deposition gases to deposit a first portion of the film over the substrate and within the gap with a first deposition process that has simultaneous deposition and sputtering components until after the gap has closed. A sufficient part of the first portion of the film is etched back to reopen the gap. Flows of second precursor deposition gases are provided to the substrate processing chamber. A second high-density plasma is formed from the flows of second precursor deposition gases to deposit a second portion of the film over the substrate and within the reopened gap with a second deposition process that has simultaneous deposition and sputtering components.

Abstract: After protective insulating films are formed on first to third active regions, the protective insulating films formed on the first and third active regions are removed. Subsequently, an insulating film to be a first gate insulating film is formed on each of the first and third active regions, and then, the protective insulating film formed on the second active region is removed. Next, an insulating film to be a second gate insulating film is formed on the second active region, and then, the insulating film to be the first gate insulating film formed on the third active region is removed. Finally, an insulating film to be a third gate insulating film is formed on the third active region.

Abstract: In a semiconductor integrated circuit device, semiconductor elements formed in active regions included in a first element formation portion (stress transition region) in a peripheral circuit formation portion are not electrically driven, while only semiconductor elements of a second element formation portion (steady stress region) are electrically driven. Therefore, the second element formation portion in the peripheral circuit formation portion is located away from an outer STI region so as to be hardly affected by compressive stress.

Abstract: A resistance defect assessment device provided on a wafer for assessing a resistance variation defect in a component of an integrated circuit device, the resistance defect assessment device including test patterns capable of measuring a resistance variation component to be the resistance variation defect in each chip area or each shot area of the wafer, wherein the number of test patterns included in one chip area or one shot area is set so that it is possible to estimate the yield of the integrated circuit device.

Abstract: After a process is performed on a substrate, the in-plane distribution over the substrate is measured. Measured data of the in-plane distribution which is obtained by the measurement is stored. A model formula of the in-plane distribution is calculated from the stored measured data. The measured data is compared with the model formula. A set of parameters of the model formula is calculated, and the calculated parameters are stored as data of the in-plane distribution over the substrate. The measured data includes measurement coordinates over the substrate. The model formula is obtained by modeling the tendency that the in-plane distribution concentrically varies and the tendency that the in-plane distribution varies along a diameter direction.