Abstract: In a semiconductor integrated circuit device, semiconductor elements formed in active regions included in a first element formation portion (stress transition region) in a peripheral circuit formation portion are not electrically driven, while only semiconductor elements of a second element formation portion (steady stress region) are electrically driven. Therefore, the second element formation portion in the peripheral circuit formation portion is located away from an outer STI region so as to be hardly affected by compressive stress.

Abstract: The invention provides a method for fabricating a semiconductor device including a concaved capacitor device having a lower electrode, a capacitor dielectric film of a perovskite type high dielectric constant or ferroelectric material formed on the lower electrode and an upper electrode formed on the capacitor dielectric film. In this method, a step of forming a conducting film to be formed into the lower electrode includes sub-steps of forming a lower conducting film by sputtering on walls and a bottom of a recess formed in an insulating film on a substrate; and forming an upper conducting film on the lower conducting film by CVD.

Abstract: A measurement substrate 100 in which a silicon oxide film 102, a polysilicon layer 103 and a titanium silicide layer 104 are formed over a silicon substrate 101 in this order is prepared. The measurement substrate 100 is irradiated with X-rays so that the proportions of three types of silicides with different compositions in the titanium silicide layer 104 are measured based on the intensity of hard X-rays emitted from oxygen in the silicon oxide film 102 and the intensity of hard X-rays emitted from titanium in the titanium silicide layer 104.

Abstract: First, a sputtering process is performed in a chamber using a target containing a plurality of elements to form at a sputtering surface of the target an erosion area different from that formed under a predetermined deposition condition for depositing a desired sputtered film. Next, the sputtered film is deposited on a surface of a sample under the predetermined deposition condition.

Abstract: After a metal layer is formed on a dielectric film, the metal layer is subjected to an oxidation process using a liquid having oxidizing power, thereby forming an adhesion layer. Then, an electrode or wiring is formed on the adhesion layer.

Abstract: A semiconductor device has a capacitance insulating film having a perovskite structure represented by the general formula ABO3 (where each of A and B is a metal element) and first and second electrodes opposed to each other with the capacitance insulating film interposed therebetween. The capacitance insulating film is formed such that the composition of the metal element A or B is higher in the region thereof adjacent the first electrode than in the other region thereof.

Abstract: A semiconductor device of the present invention includes an electrode, which is formed over a substrate and contains ruthenium. Crystal grains of ruthenium in the electrode have stepped surfaces.

Abstract: After a metal layer is formed on a dielectric film, the metal layer is subjected to an oxidation process using a liquid having oxidizing power, thereby forming an adhesion layer. Then, an electrode or wiring is formed on the adhesion layer.

Abstract: A semiconductor device including a semiconductor substrate having a main surface, an insulating layer formed on the main surface of the semiconductor substrate, and lower electrode film embedded in the insulating layer. A dielectric film embedded in the insulating layer covers the lower electrode film. An upper electrode film is embedded in the insulating layer and is opposed to the lower electrode film through the dielectric film. A conductor plug electrically connects the lower electrode film and the semiconductor substrate with each other through a lower contact hole selectively formed in the insulating layer. A conductor layer is embedded in the insulating layer and is electrically connected to the upper electrode film on a first portion defining a part of the upper surface of the conductor layer.

Abstract: In one embodiment, the process comprises depositing a CVD metal oxide layer on the substrate at a substrate temperature of less than or equal to about 480° C. and annealing the metal oxide layer. In one aspect, annealing comprises providing a first substrate temperature between abut 600° C. and 900° C., maintaining the first substrate temperature for a time period of between about 0.1 seconds and 30 minutes, providing a second substrate temperature between about 500° C. to 600° C., and maintaining the second substrate temperature for a time period of at least 10 minutes. In another embodiment, the process comprises depositing a first electrode; depositing a CVD metal oxide layer on the first electrode at a substrate temperature of less than or equal to about 480° C.; and depositing a second electrode on the oxide layer. In one aspect the metal oxide layer is annealed prior to deposition of the second electrode.

Abstract: A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) on the germanium layer, and forming a gate electrode (e.g., titanium nitride 60) on the gate dielectric. The method may comprise forming source and drain regions 64 in the substrate on either side of the gate dielectric. The germanium layer, which is preferably epitaxially grown, generally prevents formation of a low dielectric constant layer between the gate dielectric and the semiconductor substrate. The disclosed structure comprises a germanium layer 52 disposed on a semiconductor substrate (e.g. silicon 20), a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) disposed on the germanium layer, and a gate electrode (e.g., titanium nitride 60) disposed on the gate dielectric.

Abstract: A semiconductor device of the present invention includes an electrode, which is formed over a substrate and contains ruthenium. Crystal grains of ruthenium in the electrode have stepped surfaces.

Abstract: The invention provides a method for fabricating a semiconductor device including a concaved capacitor device having a lower electrode, a capacitor dielectric film of a perovskite type high dielectric constant or ferroelectric material formed on the lower electrode and an upper electrode formed on the capacitor dielectric film. In this method, a step of forming a conducting film to be formed into the lower electrode includes sub-steps of forming a lower conducting film by sputtering on walls and a bottom of a recess formed in an insulating film on a substrate; and forming an upper conducting film on the lower conducting film by CVD.

Abstract: An upper electrode film (9) is electrically connected to a part of the upper surface of a conductor layer (14) through a side wall (10). A wire (20) is connected to the conductor layer (14) through an upper contact hole (33) opening in another part of the upper surface of the conductor layer (14). Thus, over-etching is prevented in formation of the contact hole for connecting the wire to the capacitor upper electrode film.

Abstract: After a lower electrode made of Pt, for example, has been formed, impurity atoms (e.g., hydrogen atoms) which suppress decrease in stiffness of the electrode at a high temperature are introduced into the lower electrode. Then, even when the lower electrode is heated to a high temperature in an oxidizing atmosphere in the subsequent process step of forming a capacitive insulating film of e.g., BST on the lower electrode, the decrease in stiffness of the lower electrode is suppressible. Accordingly, it is possible to prevent the deformation of the lower electrode, which might otherwise result from the coagulation of metal atoms such as Pt atoms in the lower electrode.

Abstract: This invention pertains generally to the integration of dielectrics with integrated circuits, and more particularly to reaction barriers between high-k dielectrics and an underlying Group IV semiconductor layer. Applications for high permittivity memory cells and gate dielectrics are disclosed. This method has steps of providing a partially completed integrated circuit having a semiconductor layer substantially comprising silicon, where the layer has an exposed face. The method also includes forming an ultra-thin SiC reaction barrier at the exposed face, and depositing a high permittivity storage dielectric on the SiC reaction barrier. Typically, the SiC reaction barrier is less than 25 Å thick, preferably one or two monolayers of SiC.

Abstract: An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contact (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step.

Abstract: This invention pertains generally to the integration of dielectrics with integrated circuits, and more particularly to reaction barriers between high-k dielectrics and an underlying Group IV semiconductor layer. Applications for high permittivity memory cells and gate dielectrics are disclosed. This method has steps of providing a partially completed integrated circuit having a semiconductor layer substantially comprising silicon, where the layer has an exposed face. The method also includes forming an ultra-thin SiC reaction barrier at the exposed face, and depositing a high permittivity storage dielectric on the SiC reaction barrier. Typically, the SiC reaction barrier is less then 25 Å thick, preferably one or two monolayers of SiC.

Abstract: A semiconductor device of the present invention includes an electrode, which is formed over a substrate and contains ruthenium. Crystal grains of ruthenium in the electrode have stepped surfaces.

Abstract: An isolation structure which protrudes above the semiconductor surface and sidewall spacers which smooth the topography over said isolation structure.