Patents by Inventor Yasutoshi Yamada
Yasutoshi Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8558428Abstract: A windingly laminated core of a rotary electric machine, having a first number of magnetic poles in total and configured by unit cores, each of which is formed in an arc and thin plate shape and has a second number of magnetic poles, wherein a winding lamination is applied to the unit cores in a circumferential direction and in a spiral manner so as to form a cylindrical shape and a lamination thickness in an axial direction of the winding lamination is set to a predetermined thickness, includes an adjustment unit core having magnetic poles whose number is less than the second number, wherein the adjustment unit core is arranged at a start or an end of the winding lamination, in a circumferential direction, in order to align a rotational phase of the start of the winding lamination to a rotational phase of the end of the winding lamination.Type: GrantFiled: December 17, 2010Date of Patent: October 15, 2013Assignee: Aisin Seiki Kabushiki KaishaInventors: Toshiya Sugiyama, Yasutoshi Yamada
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Patent number: 8508088Abstract: A wiring component for a motor coil includes: a wire coil configured by a plurality of wire segments arranged in a circumferential direction so as to form a ring shape, each of the wire segments including an arc-shaped main-body portion made of a conductive wire rod bent in an arc shape, protruding portions formed at both end portions of the main-body portion and upright portions respectively formed at end portions of the protruding portions; an inner clip formed with a plurality of first holding portions at an outer circumferential surface of the inner clip; and an outer clip formed with a plurality of second holding portions at an inner circumferential surface of the outer clip. The inner clip and the outer clip are connected to each other so as to hold the wire coil between the first holding portions and the second holding portions.Type: GrantFiled: October 30, 2009Date of Patent: August 13, 2013Assignee: Aisin Seiko Kabushiki KaishaInventors: Toshiya Sugiyama, Jun Abiko, Yasutoshi Yamada, Hiroyuki Nagata
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Publication number: 20130107650Abstract: A device includes a plurality of restoring circuits each provided for an associated one of local bit lines, remaining one or ones of the restoring circuits other than the restoring circuit provided for the selected one of the local bit lines being configured to receive, through remaining one or ones of the local bit lines, data that is or are read out from a memory cell or cells connected to the remaining one or ones of the local bit lines, and restore, through the remaining one or ones of the local bit lines, the data into the memory cell or cells connected to the remaining one or ones of the local bit lines.Type: ApplicationFiled: September 15, 2012Publication date: May 2, 2013Inventors: Kazuhiko Kajigaya, Yasutoshi Yamada
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Patent number: 8350427Abstract: A stator of a rotary electrical machine includes a core unit configured by a plurality of core assemblies, around which wires are respectively wound to form the coils, including low voltage side terminals, which connect first ends of the coils, and a bus ring attached to the core unit so as to connect second ends of the coils to electricity supply wires by high voltage side terminals. Each terminal accommodating portion is individually formed relative to each of the core assemblies at an external side of the coils. Each of the terminal accommodating portions is filled with an insulating resin material in a state where at least one of a connecting portion of the first end and each of the low voltage side terminals and a connecting portion of the second end and each of the high voltage side terminals is accommodated within each of the terminal accommodating portions.Type: GrantFiled: March 4, 2010Date of Patent: January 8, 2013Assignee: Aisin Seiki Kabushiki KaishaInventors: Toshiya Sugiyama, Jun Abiko, Yasutoshi Yamada, Hiroyuki Nagata
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Patent number: 8320208Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.Type: GrantFiled: September 15, 2010Date of Patent: November 27, 2012Assignee: Elpida Memory, Inc.Inventors: Kazuhiko Kajigaya, Soichiro Yoshida, Yasutoshi Yamada
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Publication number: 20120275255Abstract: A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof.Type: ApplicationFiled: July 6, 2012Publication date: November 1, 2012Applicant: ELPIDA MEMORY INC.Inventors: Soichiro YOSHIDA, Kazuhiko KAJIGAYA, Yasutoshi YAMADA
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Patent number: 8238182Abstract: A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof.Type: GrantFiled: September 14, 2010Date of Patent: August 7, 2012Assignee: Elpida Memory, Inc.Inventors: Soichiro Yoshida, Kazuhiko Kajigaya, Yasutoshi Yamada
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Patent number: 8238183Abstract: A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof.Type: GrantFiled: July 1, 2011Date of Patent: August 7, 2012Assignee: Elpida Memory, Inc.Inventors: Soichiro Yoshida, Kazuhiko Kajigaya, Yasutoshi Yamada
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Patent number: 8217541Abstract: A wiring component for a motor coil includes a wire coil configured by a plurality of wire segments arranged in a circumferential direction so as to form a ring shape, each of the wire segments including an arc-shaped main-body portion made of a conductive wire rod bent in an arc shape, protruding portions formed at both end portions of the main-body portion, and upright portions respectively formed at end portions of the protruding portions in a manner of bending one of end portions of each of the protruding portions so that the upright portions protrude in a direction vertical relative to a planar surface including the main-body portion. The wire coil is arranged to form a plurality of layers, thereby forming a cylindrical shape, and the upright portions, at which the adjacent wire segments contact each other in the circumferential direction thereof, are electrically connected to each other.Type: GrantFiled: October 30, 2009Date of Patent: July 10, 2012Assignee: Aisin Seiki Kabushiki KaishaInventors: Toshiya Sugiyama, Jun Abiko, Yasutoshi Yamada, Hiroyuki Nagata
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Publication number: 20120127816Abstract: Disclosed herein is a semiconductor device comprising a memory cell, a local bit line coupled to the memory cell, a global bit line provided correspondingly to the local bit line, and a bit line control circuit coupled between the local bit line and the global bit line. The bit line control circuit includes a restoring circuit that is activated in a refresh mode to refresh data of the memory cell while being in electrical isolation from the global bit line.Type: ApplicationFiled: November 17, 2011Publication date: May 24, 2012Applicant: Elpida Memory, Inc.Inventors: Kazuhiko Kajigaya, Yasutoshi Yamada
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Publication number: 20110309725Abstract: A wiring component of a rotating electrical machine for a vehicle, includes a segment wire provided at the rotating electrical machine formed in an annular shape, made of a conductive wire rod and arranged in a circumferential direction of the rotating electrical machine, wherein the segment wire includes a main body portion having a first straight portion, a second straight portion formed at each end portion of the main body portion by bending in a radial direction of the rotating electrical machine so as to have an obtuse angle between the first straight portion and the second straight portion and an upright portion formed at the second straight portion by bending in a rotational axis direction of the rotating electrical machine, and wherein the upright portions of the segment wires being adjacent to each other are in conduction with each other.Type: ApplicationFiled: March 25, 2011Publication date: December 22, 2011Applicant: AISIN SEIKI KABUSHIKI KAISHAInventors: Toshiya SUGIYAMA, Yasutoshi YAMADA
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Publication number: 20110261631Abstract: A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof.Type: ApplicationFiled: July 1, 2011Publication date: October 27, 2011Applicant: ELPIDA MEMORY, INC.Inventors: Soichiro YOSHIDA, Kazuhiko KAJIGAYA, Yasutoshi YAMADA
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Publication number: 20110248697Abstract: A semiconductor device comprises a first circuit outputting a signal to a first signal line, a first FET applied with a driving signal and having a gate electrode connected to a first node, a second FET controlling an electrical connection between the first signal line and the first node, a third FET amplifying a signal of the first node, a second circuit precharging the first signal line, and a voltage control circuit. A gate capacitance of the first FET is controlled in response to a voltage difference between the first node and the driving signal. The voltage control circuit shifts a potential of the driving signal when the second FET is non-conductive after the signal of the first-circuit is transmitted to the first node, and performs an offset control for the driving signal so as to compensate a variation of a threshold voltage of the first FET.Type: ApplicationFiled: April 8, 2011Publication date: October 13, 2011Applicant: ELPIDA MEMORY, INC.Inventors: Kazuhiko Kajigaya, Soichiro Yoshida, Yasutoshi Yamada
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Publication number: 20110220968Abstract: A device includes a semiconductor substrate, a first local bit line formed in the semiconductor substrate and elongated in a first direction, a first insulating layer on the semiconductor substrate, a first global bit line formed on the first insulating layer, a first path formed in the first insulating layer to couple a first end of the first local bit line with the first global bit line, and a second path formed in the first insulating layer to couple a second end of the first local bit line with the first global bit line.Type: ApplicationFiled: March 7, 2011Publication date: September 15, 2011Applicant: ELPIDA MEMORY, INC.Inventors: Shinichi TAKAYAMA, Yasutoshi YAMADA
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Publication number: 20110175486Abstract: A windingly laminated core of a rotary electric machine, having a first number of magnetic poles in total and configured by unit cores, each of which is formed in an arc and thin plate shape and has a second number of magnetic poles, wherein a winding lamination is applied to the unit cores in a circumferential direction and in a spiral manner so as to form a cylindrical shape and a lamination thickness in an axial direction of the winding lamination is set to a predetermined thickness, includes an adjustment unit core having magnetic poles whose number is less than the second number, wherein the adjustment unit core is arranged at a start or an end of the winding lamination, in a circumferential direction, in order to align a rotational phase of the start of the winding lamination to a rotational phase of the end of the winding lamination.Type: ApplicationFiled: December 17, 2010Publication date: July 21, 2011Applicant: AISIN SEIKI KABUSHIKI KAISHAInventors: Toshiya SUGIYAMA, Yasutoshi Yamada
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Patent number: 7933141Abstract: In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes.Type: GrantFiled: April 1, 2009Date of Patent: April 26, 2011Assignee: Elpida Memory, Inc.Inventors: Kazuhiko Kajigaya, Soichiro Yoshida, Tomonori Sekiguchi, Riichiro Takemura, Yasutoshi Yamada
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Publication number: 20110063892Abstract: A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes.Type: ApplicationFiled: September 15, 2010Publication date: March 17, 2011Applicant: ELPIDA MEMORY, INC.Inventors: Kazuhiko KAJIGAYA, Soichiro YOSHIDA, Yasutoshi YAMADA
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Publication number: 20110063935Abstract: A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof.Type: ApplicationFiled: September 14, 2010Publication date: March 17, 2011Applicant: ELPIDA MEMORY, INC.Inventors: Soichiro YOSHIDA, Kazuhiko KAJIGAYA, Yasutoshi YAMADA
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Patent number: 7903449Abstract: A semiconductor memory device (e.g. DRAM) is constituted of a memory cell array including a plurality of memory cells, a plurality of word line drivers, a plurality of sense amplifiers, and a plurality of dummy capacitors. The memory cells, each of which includes a transistor and a capacitor, are positioned at intersections between the word lines and the bit lines. The first electrodes of the capacitors are connected to the transistors in the memory cells. The first electrodes of the dummy capacitors are connected together and are supplied with a second potential (e.g. VDD or VSS). The second electrodes of the dummy capacitors are connected together with the second electrodes of the capacitors of the memory cells and are supplied with a first potential (e.g. VPL). The dummy capacitors serve as smoothing capacitances for the plate voltage VPL so as to reduce plate noise.Type: GrantFiled: June 16, 2009Date of Patent: March 8, 2011Assignee: Elpida Memory, Inc.Inventors: Kazuhiko Kajigaya, Soichiro Yoshida, Tomonori Sekiguchi, Riichiro Takemura, Yasutoshi Yamada
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Publication number: 20100244597Abstract: A stator of a rotary electrical machine includes a core unit configured by a plurality of core assemblies, around which wires are respectively wound to form the coils, including low voltage side terminals, which connect first ends of the coils, and a bus ring attached to the core unit so as to connect second ends of the coils to electricity supply wires by high voltage side terminals. Each terminal accommodating portion is individually formed relative to each of the core assemblies at an external side of the coils. Each of the terminal accommodating portions is filled with an insulating resin material in a state where at least one of a connecting portion of the first end and each of the low voltage side terminals and a connecting portion of the second end and each of the high voltage side terminals is accommodated within each of the terminal accommodating portions.Type: ApplicationFiled: March 4, 2010Publication date: September 30, 2010Applicant: AISIN SEIKI KABUSHIKI KAISHAInventors: Toshiya SUGIYAMA, Jun Abiko, Yasutoshi Yamada, Hiroyuki Nagata