Patents by Inventor Yasuyuki Ogawa

Yasuyuki Ogawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140367677
    Abstract: This semiconductor device (100A) includes: a substrate (2); a gate electrode (3) formed on the substrate (2); a gate insulating layer (4) formed over the gate electrode (3); an oxide semiconductor layer (5) formed on the gate insulating layer (4); source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5); a first transparent electrode (7) electrically connected to the drain electrode (6d); an interlayer insulating layer (8) including a dielectric layer (8a) formed over the source and drain electrodes (6s, 6d); and a second transparent electrode (9) formed on the interlayer insulating layer (8). At least a portion of the second transparent electrode (9) overlaps with the first transparent electrode (7) with the dielectric layer (8a) interposed between them, and the oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.
    Type: Application
    Filed: January 24, 2013
    Publication date: December 18, 2014
    Inventors: Tadayoshi Miyamoto, Kazuatsu Ito, Shigeyasu Mori, Mitsunobu Miyamoto, Yasuyuki Ogawa, Makoto Nakazawa, Takuya Matsuo, Seiichi Uchida
  • Publication number: 20140361295
    Abstract: A semiconductor device (100A) includes a substrate (2), an oxide semiconductor layer (5) formed on the substrate (2), source and drain electrodes (6s, 6d) electrically connected to the oxide semiconductor layer (5), a first transparent electrode (7) electrically connected to the drain electrode (6d), a dielectric layer (8) formed on the source and drain electrodes (6s, 6d), and a second transparent electrode (9) formed on the dielectric layer (8). The upper and/or lower surface(s) of the first transparent electrode (7) contacts with a reducing insulating layer (8a) with the property of reducing an oxide semiconductor included in the oxide semiconductor layer (5). The second transparent electrode (9) overlaps at least partially with the first transparent electrode (7) via the dielectric layer (8). The oxide semiconductor layer (5) and the first transparent electrode (7) are formed out of the same oxide film.
    Type: Application
    Filed: January 24, 2013
    Publication date: December 11, 2014
    Inventors: Tadayoshi Miyamoto, Kazuatsu Ito, Shigeyasu Mori, Mitsunobu Miyamoto, Yasuyuki Ogawa, Makoto Nakazawa, Seiichi Uchida, Takuya Matsuo
  • Publication number: 20140320479
    Abstract: At the time of partial drive, the levels of voltages applied to data lines SL1 to SLn are switched according to a rewrite frequency set for each region of a display screen. For example, in a still-image display region with a relatively low rewrite frequency, the levels of the voltages applied to the data lines SL1 to SLn are set to be higher than those for a moving-image display region with a relatively high rewrite frequency. By this, the same effect as that obtained when a counter voltage is switched according to the rewrite frequency can be obtained. Thus, flicker occurring in each region of the display screen can be suppressed.
    Type: Application
    Filed: September 20, 2012
    Publication date: October 30, 2014
    Inventors: Seiji Kaneko, Kaoru Yamamoto, Yasuyuki Ogawa, Kohhei Tanaka, Seiichi Uchida, Yutaka Takamaru, Shigeyasu Mori
  • Publication number: 20140307109
    Abstract: A recording medium removable from a host device includes a wireless communication unit for performing wireless communication with an external device different from the host device. The recording medium includes an image transmission control unit which transmits image data to the external device via the wireless communication established by the wireless communication unit by using an image transmission protocol. The recording medium switches which of the image transmission control unit of the recording medium and an image transmission control unit of the host device is used to communicate with the external device via the wireless communication unit.
    Type: Application
    Filed: November 22, 2012
    Publication date: October 16, 2014
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Masashi Yoshida, Yasuyuki Ogawa, Satoshi Ogiwara, Takashi Aizawa
  • Publication number: 20140267464
    Abstract: In a display control circuit (200) of a display device, an image pattern detection portion (230) detects whether an image is an anti-flicker pattern or not, and when it is an anti-flicker pattern, a backlight source is driven (typically, such that its luminance changes in the opposite phase relative to luminance changes that would occur), on the basis of predicted values, which are predetermined so as to compensate for the luminance changes that would occur. Moreover, the backlight is not turned on during the scanning period. As a result, flicker due to current leakage, etc., can be reduced or eliminated in a display device for which a scanning period and a scan stop period are set.
    Type: Application
    Filed: October 31, 2012
    Publication date: September 18, 2014
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takamaru, Seiji Kaneko, Yasuyuki Ogawa, Kaoru Yamamoto, Kohhei Tanaka, Seiichi Uchida, Noriaki Yamaguchi, Shigeyasu Mori
  • Publication number: 20140176845
    Abstract: In order to suppress crosstalk between a pixel electrode and a source line to reduce flicker, an LCD device includes: gate lines 102 and source lines 105 which are provided in a grid pattern; pixel electrodes 111 arranged in a matrix pattern so as to correspond to intersections of the gate lines and the source lines; a transparent auxiliary capacitor electrode 109; and switching elements 121 configured to apply an image signal voltage supplied from the source line 105 to the pixel electrode 111 according to a scanning signal applied from the gate line 102. The switching element 121 is formed by using an oxide semiconductor layer 104, and the transparent auxiliary capacitor electrode 109 is provided between the source line 105 and the pixel electrode 111.
    Type: Application
    Filed: August 3, 2012
    Publication date: June 26, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Seiichi Uchida, Seiji Kaneko, Yasuyuki Ogawa, Kaoru Yamamoto, Kohhei Tanaka, Yutaka Takamaru, Shigeyasu Mori
  • Publication number: 20140168182
    Abstract: Provided is a liquid crystal display device with reduced power consumption employing a CS drive method. A CS driver (500) consists of a CS shift register (510) and a CS output portion (520). The CS shift register (510) outputs control signals (COUT(1) to COUT(m)) in accordance with a CS clock signal CCK. The CS output portion (520) outputs auxiliary capacitance signals (CSS(1) to CSS(m)) in accordance with the control signals (COUT(1) to COUT(m)), respectively. An idle period (T2) is set following a scanning period (T1). During the idle period (T2), the CS driver (500) is driven in accordance with the CS clock signal (CCK) at an idle-period CS frequency (fcck2). The idle-period CS frequency (fcck2) is lower than a scanning-period CS frequency (fcck1).
    Type: Application
    Filed: July 25, 2012
    Publication date: June 19, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kaoru Yamamoto, Seiji Kaneko, Yasuyuki Ogawa, Kohhei Tanaka, Seiichi Uchida, Yutaka Takamaru, Shigeyasu Mori
  • Publication number: 20140145996
    Abstract: A semiconductor layer for an active element included in each of a plurality of pixels in a display section is constituted by an oxide layer containing at least one element selected from the group consisting of In, Ga, and Zn. There is provided, for the display section, a liquid crystal panel's timing controller (13) configured to carry out control so that (i) a length of a first period during which image data is written is not more than twice that of the second period and/or (ii) one (1) frame period is longer than 16.7 msec.
    Type: Application
    Filed: July 27, 2012
    Publication date: May 29, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yasuhiro Sugita, Kazutoshi Kida, Shinji Yamagishi, Yuhji Yashiro, Hiroyuki Ogawa, Shigeyasu Mori, Seiji Kaneko, Yasuyuki Ogawa, Kaoru Yamamoto, Kohhei Tanaka, Seiichi Uchida, Yutaka Takamaru
  • Patent number: 8704819
    Abstract: There is provided a display device capable of displaying an image that barely changes with low power consumption on the basis of video data included in a transmitted command, and there is also provided a method for driving the same. A display timing controller (31) determines every frame period whether or not an externally transmitted command includes updated video data. As a result, when it is determined that no updated video data is included, screen refreshing is paused by not reading video data stored in frame memory (36). Moreover, when it is determined that updated video data is included, the screen refreshing is performed by reading video data stored in the frame memory (36).
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: April 22, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuyuki Ogawa, Seiji Kaneko, Kaoru Yamamoto, Kohhei Tanaka, Seiichi Uchida, Yutaka Takamaru, Shigeyasu Mori
  • Patent number: 8698726
    Abstract: There is provided an SSD display device with reduced power consumption. A selection circuit (400) consists of k selection blocks (410(1) to 410(k)). Each selection block consists of three thin-film transistors. The three thin-film transistors respectively have three phases of selection control signal (CT) provided to their gate terminals. A scanning period (T1) is provided and followed by an idle period (T2). In the idle period (T2), the three thin-film transistors in each selection block are brought into ON state in accordance with selection control signals (CT) at an idle period frequency (fck2). The idle period frequency (fck2) is lower than a scanning period frequency (fck1).
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: April 15, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kaoru Yamamoto, Seiji Kaneko, Yasuyuki Ogawa, Kohhei Tanaka, Seiichi Uchida, Yutaka Takamaru, Shigeyasu Mori
  • Patent number: 8659678
    Abstract: A system, method and computer program product for arranging digital data in a file in an apparatus-implemented system, is disclosed. One or more pages are generated, where each page includes: i. a mode field containing a camera operation mode, ii. an image data field containing image data, iii. an offset field containing an offset to a next page in the file, and a total size field containing a page size. Each page is recorded in the file using the same format.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: February 25, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuyuki Ogawa, Akira Suga, Makoto Gohda
  • Publication number: 20140022234
    Abstract: There is provided a display device capable of displaying an image that barely changes with low power consumption on the basis of video data included in a transmitted command, and there is also provided a method for driving the same. A display timing controller (31) determines every frame period whether or not an externally transmitted command includes updated video data. As a result, when it is determined that no updated video data is included, screen refreshing is paused by not reading video data stored in frame memory (36). Moreover, when it is determined that updated video data is included, screen refreshing is performed by reading video data stored in the frame memory (36).
    Type: Application
    Filed: August 29, 2012
    Publication date: January 23, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yasuyuki Ogawa, Seiji Kaneko, Kaoru Yamamoto, Kohhei Tanaka, Seiichi Uchida, Yutaka Takamaru, Shigeyasu Mori
  • Publication number: 20130314390
    Abstract: There is provided an SSD display device with reduced power consumption. A selection circuit (400) consists of k selection blocks (410(1) to 410(k)). Each selection block consists of three thin-film. transistors. The three thin-film transistors respectively have three phases of selection control signal (CT) provided to their gate terminals. A scanning period (T1) is provided and followed by an idle period (T2). In the idle period (T2), the three thin-film transistors in each selection block are brought into ON state in accordance with selection control signals (CT) at an idle period frequency (fck2). The idle period frequency (fck2) is lower than a scanning period frequency (fck1).
    Type: Application
    Filed: July 25, 2012
    Publication date: November 28, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Kaoru Yamamoto, Seiji Kaneko, Yasuyuki Ogawa, Kohhei Tanaka, Seiichi Uchida, Yutaka Takamaru, Shigeyasu Mori
  • Publication number: 20130215345
    Abstract: The sum of parasitic capacitances CG and CB, which are formed between each of two source signal lines 25SLG and 25SLB that constitute any of a first color to a third color pixel, and a pixel electrode 27G corresponding to the pixel, is set so as to be smaller in the first color pixel than in other color pixels.
    Type: Application
    Filed: October 20, 2011
    Publication date: August 22, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Seiji Kaneko, Yasuyuki Ogawa
  • Patent number: 8487922
    Abstract: A buffer circuit drives a capacitive load based on a voltage Vin. In a setup period, switches are in an ON state, and in a drive period, a switch is in an ON state. A voltage comparison unit compares the voltage Vin in the setup period and a voltage Vout in a drive period to output a comparison result voltage. A push-pull output unit includes a TFT for charge and a TFT for discharge. A drive control unit controls the TFTs to be in an OFF state in the setup period, and in the drive period, selectively controls the TFTs to be in an ON state in accordance with the comparison result voltage. If Vout<Vin, the comparison result voltage rises, the TFT becomes in an ON state, a voltage at a node falls, the TFT becomes in the ON state, and the voltage Vout rises. Thus, there is a provided a small-sized capacitive load drive circuit with low power consumption and robust against process variation.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: July 16, 2013
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Christopher Brown, Yasuyuki Ogawa
  • Patent number: 8466977
    Abstract: An image data management apparatus includes a unit adapted to display different types of plural frames (such as an in-focus frame and a face frame) at the same time in a manner capable of selectively changing both of those frames by a user operation such that an in-focus frame portion and a face frame portion can be easily confirmed.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: June 18, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobukazu Yoshida, Yasuyuki Ogawa, Chiyumi Niwa, Hiroyuki Ogino, Koji Sudo
  • Publication number: 20130100007
    Abstract: A shift register 10 is configured such that m unit circuits 11 each including a shift unit 12 and three buffer units 13r, 13g, and 13b are in a multi-stage cascade connection and that 3m signals in total including three signals from each stage are outputted. The m shift units 12 perform a shift operation, and a first signal Y is outputted from each stage. When a clock signal CK is at a high level, the first signal Y rises higher than a normal high level due to bootstrapping. The buffer unit 13r controls an output signal YR to be at a high level based on the buffer control signal CR and the first signal Y. A buffer control circuit 7 controls buffer control signals CR, CG, and CB to be at a high level for a time period shorter than a half cycle of the clock signal. With this, a shift register with a reduced circuit amount and low power consumption is provided.
    Type: Application
    Filed: April 4, 2011
    Publication date: April 25, 2013
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Kaoru Yamamoto, Yasuyuki Ogawa
  • Patent number: 8368776
    Abstract: A system, method and computer program product for arranging digital data in a file in an apparatus-implemented system, is disclosed. One or more pages are generated, where each page includes: i. a mode field containing a camera operation mode, ii. an image data field containing image data, iii. an offset field containing an offset to a next page in the file, and a total size field containing a page size. Each page is recorded in the file using the same format.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: February 5, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasuyuki Ogawa, Akira Suga, Makoto Gohda
  • Publication number: 20130021295
    Abstract: A display device with a touch panel function includes a pressure sensor as a first sensor for detecting presence/absence of pressurization on an input screen, an electrostatic capacitance touch panel as a second sensor for detecting a contact position on the input screen, whose power consumption for waiting in a detectable state is higher than power consumption of the first sensor, and a control unit for switching the second sensor into the detectable state when presence of pressurization is detected by the first sensor. The input screen also serves as a display screen.
    Type: Application
    Filed: March 16, 2011
    Publication date: January 24, 2013
    Inventors: Tomohiro Kimura, Keiichi Fukuyama, Yasuyuki Ogawa
  • Patent number: 8314857
    Abstract: A data recording apparatus holds device state information which is updated according to use of the apparatus and represents a use state of the apparatus, and device identification information unique to the apparatus. Upon recording data, the data recording apparatus acquires information associated with generation of recording data, which is different from the device state information, as recording information, in association with the recording data. The apparatus generates unique identification information of the recording data based on the device identification information, the device state information, and the recording information, and records a file including the recording data and the unique identification information in a recording medium.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: November 20, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yuichi Nakase, Yasuyuki Ogawa