Patents by Inventor Yasuyuki Yanase

Yasuyuki Yanase has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8288865
    Abstract: A semiconductor module includes: an insulating resin layer; a wiring layer which is provided on one main surface of the insulating resin layer and which includes an external connection region; bump electrodes which are electrically connected to the wiring layer and each of which is formed such that it protrudes from the wiring layer toward the insulating resin layer; a semiconductor device which is provided on the other main surface of the insulating resin layer and which includes device electrodes connected to the bump electrode; and a wiring protection layer provided on the wiring layer and the insulating resin layer so as to expose the external connection region. In the semiconductor module, the outer edge portion of the wiring protection layer is in contact with the external edge portion of the semiconductor device such that it shields at least a part of the semiconductor resin layer at the side edge.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: October 16, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Atsunobu Suzuki, Koichi Saito, Yasuyuki Yanase, Takahiro Fujii
  • Patent number: 8278566
    Abstract: A device mounting board includes: an insulating resin layer; a wiring layer disposed on one main surface of the insulating resin layer; and a bump electrode connected electrically to the wiring layer and protruding on a side of the insulating resin layer from the wiring layer. A side surface of the bump electrode is curved inwardly toward the center axis of the bump electrode as viewed in a cross section including the center axis of the bump electrode, and the radius of curvature of the side surface changes continuously from a wiring layer end to a head end of the bump electrode.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: October 2, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hajime Kobayashi, Yasuyuki Yanase, Tetsuya Yamamoto, Yoshio Okayama
  • Patent number: 8274148
    Abstract: A first circuit element and a second element are mounted with their electrode forming surfaces facing a wiring layer. A first bump electrode formed integrally with the wiring layer on one face substantially penetrates a first insulating resin layer. A gold plating layer covering an element electrode of the first circuit element and a gold plating layer disposed on top of the first bump electrode are bonded together by Au—Au bonding. A second bump electrode formed integrally with the wiring layer on one face substantially penetrates the first and the second insulating resin layer. A gold plating layer covering an element electrode of the second circuit element and a gold plating layer disposed on top of the second bump electrode are bonded together by Au—Au bonding.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: September 25, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasuyuki Yanase, Atsunobu Suzuki, Yoshio Okayama
  • Patent number: 8242598
    Abstract: A semiconductor module includes: an insulating resin layer; a wiring layer which is provided on one main surface of the insulating resin layer and which includes an external connection region; bump electrodes which are electrically connected to the wiring layer and each of which is formed such that it protrudes from the wiring layer toward the insulating resin layer; a semiconductor device which is provided on the other main surface of the insulating resin layer and which includes device electrodes connected to the bump electrode; and a wiring protection layer provided on the wiring layer and the insulating resin layer so as to expose the external connection region. In the semiconductor module, the outer edge portion of the wiring protection layer is in contact with the external edge portion of the semiconductor device such that it shields at least a part of the semiconductor resin layer at the side edge.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: August 14, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Atsunobu Suzuki, Koichi Saito, Yasuyuki Yanase, Takahiro Fujii
  • Patent number: 8237258
    Abstract: A semiconductor module includes a device mounting board and a semiconductor device mounted on the device mounting board. The device mounting board includes an insulating resin layer, a wiring layer provided on one main surface of the insulating resin layer, and bump electrodes, electrically connected to the wiring layer, which are protruded from the wiring layer toward the insulating resin layer. The semiconductor device has device electrodes which are disposed counter to a semiconductor substrate and the bump electrodes, respectively. The surface of a metallic layer provided on the device electrode lies on the same plane as the surface of a protective layer.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: August 7, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kouichi Saitou, Yoshio Okayama, Yasuyuki Yanase, Takahiro Fujii
  • Patent number: 8129846
    Abstract: A board adapted to mount an electronic device includes an insulating resin layer, a wiring layer of a predetermined pattern provided on one surface of the insulating resin layer, a bump electrode provided on an insulating-resin-layer-side surface of the wiring layer, and a covering, formed of a metal layer, which covers a top surface of the bump electrode and a region, at a side surface of the bump electrode, continuous with the top surface excluding a region in contact with the wiring layer.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: March 6, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Tetsuya Yamamoto, Yoshio Okayama, Yasuyuki Yanase
  • Publication number: 20110186993
    Abstract: A semiconductor element mounted on an insulating resin layer formed on a wiring layer is sealed by a sealing resin. On the wiring layer, a protruding electrode protruding to the side of the semiconductor element and a protruding section are integrally formed with the wiring layer, respectively. The protruding electrode is electrically connected to an element electrode of the semiconductor element by penetrating the insulating resin layer. The protruding section is arranged to surround the semiconductor element along the four sides of the semiconductor element, and is embedded in the sealing resin up to a position above a section where the protruding electrode and the element electrode are bonded.
    Type: Application
    Filed: July 29, 2009
    Publication date: August 4, 2011
    Inventors: Hajime Kobayashi, Mayumi Nakasato, Ryosuke Usui, Yasuyuki Yanase, Koichi Saito
  • Patent number: 7989359
    Abstract: A semiconductor substrate having on its surface an electrode of a semiconductor device and a pattern unit is prepared. A copper plate is formed provided with a first principle surface having a bump and a second principle surface, opposite to the first principle surface, having a trench. By adjusting the position of the copper plate so that a pattern unit and the corresponding trench have a predetermined positional relation, the bump and the electrode are aligned, the first principle surface of the copper plate and a semiconductor substrate are pressure-bonded via an insulating layer, and the bump and the electrode become connected electrically while the bump penetrating the insulating layer. A predetermined rewiring pattern is formed on the side of the second principle surface.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: August 2, 2011
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yoshio Okayama, Yasuyuki Yanase
  • Publication number: 20110074025
    Abstract: An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.
    Type: Application
    Filed: December 6, 2010
    Publication date: March 31, 2011
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Yasuyuki Yanase, Yoshio Okayama, Kiyoshi Shibata, Yasunori Inoue, Hideki Mizuhara, Ryosuke Usui, Tetsuya Yamamoto, Masurao Yoshii
  • Patent number: 7855452
    Abstract: An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: December 21, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasuyuki Yanase, Yoshio Okayama, Kiyoshi Shibata, Yasunori Inoue, Hideki Mizuhara, Ryosuke Usui, Tetsuya Yamamoto, Masurao Yoshii
  • Publication number: 20100276800
    Abstract: A first circuit element and a second element are mounted with their electrode forming surfaces facing a wiring layer. A first bump electrode formed integrally with the wiring layer on one face substantially penetrates a first insulating resin layer. A gold plating layer covering an element electrode of the first circuit element and a gold plating layer disposed on top of the first bump electrode are bonded together by Au—Au bonding. A second bump electrode formed integrally with the wiring layer on one face substantially penetrates the first and the second insulating resin layer. A gold plating layer covering an element electrode of the second circuit element and a gold plating layer disposed on top of the second bump electrode are bonded together by Au—Au bonding.
    Type: Application
    Filed: March 19, 2010
    Publication date: November 4, 2010
    Inventors: Yasuyuki YANASE, Atsunobu Suzuki, Yoshio Okayama
  • Publication number: 20100207270
    Abstract: A semiconductor module is of a structure such that a wiring layer, an insulating resin layer and a semiconductor device are stacked in this order by bonding them together with compression. In the wiring layer, bump electrodes each having a base and a tip portion are provided in positions corresponding respectively to device electrodes of the semiconductor device. The bump electrodes penetrate the insulating resin layer and are electrically coupled to the corresponding device electrodes.
    Type: Application
    Filed: September 25, 2008
    Publication date: August 19, 2010
    Inventors: Yasuyuki Yanase, Yoshio Okayama, Ryosuke Usui
  • Publication number: 20100193946
    Abstract: A semiconductor module includes: an insulating resin layer; a wiring layer which is provided on one main surface of the insulating resin layer and which includes an external connection region; bump electrodes which are electrically connected to the wiring layer and each of which is formed such that it protrudes from the wiring layer toward the insulating resin layer; a semiconductor device which is provided on the other main surface of the insulating resin layer and which includes device electrodes connected to the bump electrode; and a wiring protection layer provided on the wiring layer and the insulating resin layer so as to expose the external connection region. In the semiconductor module, the outer edge portion of the wiring protection layer is in contact with the external edge portion of the semiconductor device such that it shields at least a part of the semiconductor resin layer at the side edge.
    Type: Application
    Filed: January 29, 2010
    Publication date: August 5, 2010
    Inventors: Atsunobu Suzuki, Koichi Saito, Yasuyuki Yanase, Takahiro Fujii
  • Publication number: 20100140797
    Abstract: A device mounting board is provided with: an insulating resin layer; a wiring layer provided on one major surface of the insulating resin layer; and a bump electrode electrically connected to the wiring layer and configured to be projected from the wiring layer toward the insulating resin layer. The bump electrode has an approximately convex-shaped top surface and at least the peripheral area on the top surface thereof is curve-shaped.
    Type: Application
    Filed: November 27, 2009
    Publication date: June 10, 2010
    Inventors: Yasuyuki YANASE, Koichi SAITO
  • Publication number: 20090250711
    Abstract: To also intend the improvement of light-emitting efficiency by microcrystallizing light-emitting layer while utilizing vapor-phase growth method that is advantageous for improving crystal quality, and the like. 4 for forming light-emitting layer comprises a substrate single-crystal substrate 1, and an oriented fine crystal layer 3 being formed on the single-crystal substrate 4. One of the crystal axes of respective crystals, which constitute the oriented microcrystal layer 3, is oriented in a specific direction with respect to the single-crystal substrate 1, and an average of the crystal grain diameters of the respective crystals, which constitute the oriented microcrystal layer 3, is adapted to being 1-1,000 nm.
    Type: Application
    Filed: August 24, 2006
    Publication date: October 8, 2009
    Inventors: Akira Kiyama, Rentaro Mori, Hiroya Inaoka, Masayuki Ichiyanagi, Nobuhiko Sawaki, Yoshio Honda, Yasuyuki Yanase
  • Publication number: 20090218686
    Abstract: A semiconductor module includes a device mounting board and a semiconductor device mounted on the device mounting board. The device mounting board includes an insulating resin layer, a wiring layer provided on one main surface of the insulating resin layer, and bump electrodes, electrically connected to the wiring layer, which are protruded from the wiring layer toward the insulating resin layer. The semiconductor device has device electrodes which are disposed counter to a semiconductor substrate and the bump electrodes, respectively. The surface of a metallic layer provided on the device electrode lies on the same plane as the surface of a protective layer.
    Type: Application
    Filed: February 27, 2009
    Publication date: September 3, 2009
    Inventors: Kouichi SAITOU, Yoshio OKAYAMA, Yasuyuki YANASE, Takahiro FUJII
  • Publication number: 20090196011
    Abstract: A device mounting board includes: an insulating resin layer; a wiring layer disposed on one main surface of the insulating resin layer; and a bump electrode connected electrically to the wiring layer and protruding on a side of the insulating resin layer from the wiring layer. A side surface of the bump electrode is curved inwardly toward the center axis of the bump electrode as viewed in a cross section including the center axis of the bump electrode, and the radius of curvature of the side surface changes continuously from a wiring layer end to a head end of the bump electrode.
    Type: Application
    Filed: February 2, 2009
    Publication date: August 6, 2009
    Inventors: Hajime KOBAYASHI, Yasuyuki Yanase, Tetsuya Yamamoto, Yoshio Okayama
  • Publication number: 20090183906
    Abstract: A substrate for mounting a device includes: an insulating resin layer made of an insulating resin; a wiring layer provided on one major surface of the insulating resin layer; and a projected portion that projects toward the direction opposite to the insulating resin layer from the wiring layer, and that is used for supporting a low-melting metal ball, while being connected to the wiring layer electrically. The wiring layer and the projected portion are formed into one body.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 23, 2009
    Inventors: Hajime KOBAYASHI, Yasuyuki Yanase, Yoshio Okayama, Yasunori Inoue
  • Publication number: 20090121350
    Abstract: A board adapted to mount an electronic device includes an insulating resin layer, a wiring layer of a predetermined pattern provided on one surface of the insulating resin layer, a bump electrode provided on an insulating-resin-layer-side surface of the wiring layer, and a covering, formed of a metal layer, which covers a top surface of the bump electrode and a region, at a side surface of the bump electrode, continuous with the top surface excluding a region in contact with the wiring layer.
    Type: Application
    Filed: November 7, 2008
    Publication date: May 14, 2009
    Inventors: Tetsuya YAMAMOTO, Yoshio OKAYAMA, Yasuyuki YANASE
  • Publication number: 20080284012
    Abstract: A semiconductor substrate having on its surface an electrode of a semiconductor device and a pattern unit is prepared. A copper plate is formed provided with a first principle surface having a bump and a second principle surface, opposite to the first principle surface, having a trench. By adjusting the position of the copper plate so that a pattern unit and the corresponding trench have a predetermined positional relation, the bump and the electrode are aligned, the first principle surface of the copper plate and a semiconductor substrate are pressure-bonded via an insulating layer, and the bump and the electrode become connected electrically while the bump penetrating the insulating layer. A predetermined rewiring pattern is formed on the side of the second principle surface.
    Type: Application
    Filed: January 30, 2008
    Publication date: November 20, 2008
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Yoshio Okayama, Yasuyuki Yanase