Patents by Inventor Yen-Chen Chen

Yen-Chen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190006519
    Abstract: A semiconductor device includes an oxide semiconductor layer, disposed over a substrate. A source electrode of a metal nitride is disposed on the oxide semiconductor layer. A drain electrode of the metal nitride is disposed on the oxide semiconductor layer. A metal-nitride oxidation layer is formed on a surface of the source electrode and the drain electrode. A ratio of a thickness of the metal-nitride oxidation layer to a thickness of the drain electrode or the source electrode is equal to or less than 0.2.
    Type: Application
    Filed: June 29, 2017
    Publication date: January 3, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Yen-Chen Chen, Xiao Wu, Hai Tao Liu, Ming Hua Du, Shouguo Zhang, Yao-Hung Liu, Chin-Fu Lin, Chun-Yuan Wu
  • Publication number: 20180331193
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.
    Type: Application
    Filed: July 25, 2018
    Publication date: November 15, 2018
    Inventors: Shih-Min Chou, Yun-Tzu Chang, Wei-Ning Chen, Wei-Ming Hsiao, Chia-Chang Hsu, Kuo-Chih Lai, Yang-Ju Lu, Yen-Chen Chen, Chun-Yao Yang
  • Publication number: 20180261675
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.
    Type: Application
    Filed: March 8, 2017
    Publication date: September 13, 2018
    Inventors: Shih-Min Chou, Yun-Tzu Chang, Wei-Ning Chen, Wei-Ming Hsiao, Chia-Chang Hsu, Kuo-Chih Lai, Yang-Ju Lu, Yen-Chen Chen, Chun-Yao Yang
  • Patent number: 10074725
    Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes an isolation layer, a gate dielectric layer, a tantalum nitride layer, a tantalum oxynitride layer, an n type work function metal layer and a filling metal. The isolation layer is formed on a substrate, and the isolation layer has a first gate trench. The gate dielectric layer is formed in the first gate trench, the tantalum nitride layer is formed on the gate dielectric layer, and the tantalum oxynitride layer is formed on the tantalum nitride layer. The n type work function metal layer is formed on the tantalum oxynitride layer in the first gate trench, and the filling metal is formed on the n type work function metal layer in the first gate trench.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: September 11, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Min Chou, Yun-Tzu Chang, Wei-Ning Chen, Wei-Ming Hsiao, Chia-Chang Hsu, Kuo-Chih Lai, Yang-Ju Lu, Yen-Chen Chen, Chun-Yao Yang
  • Publication number: 20180138263
    Abstract: A semiconductor structure includes a capacitor. The capacitor includes a bottom electrode, a first high-k dielectric layer, a second high-k dielectric layer and a top electrode. The bottom electrode includes a first layer and a second layer disposed on the first layer. The bottom electrode is formed of TiN. The first layer has a crystallization structure. The second layer has an amorphous structure. The first high-k dielectric layer is disposed on the bottom electrode. The first high-k dielectric layer is formed of TiO2. The second high-k dielectric layer is disposed on the first high-k dielectric layer. The second high-k dielectric layer is formed of a material different from TiO2. The top electrode is disposed on the second high-k dielectric layer.
    Type: Application
    Filed: November 14, 2016
    Publication date: May 17, 2018
    Inventors: Ko-Wei Lin, Yen-Chen Chen, Chin-Fu Lin, Chun-Yuan Wu, Chun-Ling Lin
  • Patent number: 9966425
    Abstract: A method for fabricating a metal-insulator-metal (MIM) capacitor includes the steps of: forming a capacitor bottom metal (CBM) layer on a material layer; forming a silicon layer on the CBM layer; forming a capacitor dielectric layer on the silicon layer; and forming a capacitor top metal (CTM) layer on the capacitor dielectric layer.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: May 8, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Jen-Po Huang, Chin-Fu Lin, Bin-Siang Tsai, Xu Yang Shen, Seng Wah Liau, Yen-Chen Chen, Ko-Wei Lin, Chun-Ling Lin, Kuo-Chih Lai, Ai-Sen Liu, Chun-Yuan Wu, Yang-Ju Lu
  • Patent number: 9789448
    Abstract: Embodiments of a process for treating a fluid are provided. The process for treating a fluid includes supplying a first fluid to a circulating chamber and introducing a first gas to the first fluid. A portion of the first gas is dissolved in the first fluid and a portion of the first gas is held in a head space portion of the circulating chamber. The process further includes mixing a portion of the first fluid drawn out from the circulating chamber and a portion of the first gas drawn out from the head space portion to form a mixture. The process further includes spraying the mixture back into the circulating chamber by a two-fluid nozzle. In addition, the first gas is further dissolved into the first fluid to form a high conductivity fluid. The process further includes draining the high conductivity fluid from the circulating chamber.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shing-Fong Wu, Yung-Ti Hung, Shih-Pao Chien, Yen-Chen Chen
  • Patent number: 9728467
    Abstract: A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.
    Type: Grant
    Filed: October 12, 2015
    Date of Patent: August 8, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Yun-Tzu Chang, Shih-Min Chou, Kuo-Chih Lai, Ching-Yun Chang, Hsiang-Chieh Yen, Yen-Chen Chen, Yang-Ju Lu, Nien-Ting Ho, Chi-Mao Hsu
  • Patent number: 9691704
    Abstract: A semiconductor structure comprises a first wire level, a second wire level and a via level. The first wire level comprises a first conductive feature. The second wire level is disposed on the first wire level. The second wire level comprises a second conductive feature and a third conductive feature. The via level is disposed between the first wire level and the second wire level. The via level comprises a via connecting the first conductive feature and the second conductive feature. There is a first air gap between the first conductive feature and the second conductive feature. There is a second air gap between the second conductive feature and the third conductive feature. The first air gap and the second air gap are linked.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: June 27, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Chia-Chang Hsu, Nien-Ting Ho, Ching-Yun Chang, Yen-Chen Chen, Shih-Min Chou, Yun-Tzu Chang, Yang-Ju Lu, Wei-Ming Hsiao, Wei-Ning Chen
  • Publication number: 20170148891
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first region, a second region, a third region, and a fourth region; forming a tuning layer on the second region; forming a first work function metal layer on the first region and the tuning layer of the second region; forming a second work function metal layer on the first region, the second region, and the fourth region; and forming a top barrier metal (TBM) layer on the first region, the second region, the third region, and the fourth region.
    Type: Application
    Filed: November 24, 2015
    Publication date: May 25, 2017
    Inventors: Kuo-Chih Lai, Yun-Tzu Chang, Wei-Ming Hsiao, Nien-Ting Ho, Shih-Min Chou, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Kuan-Chun Lin, Chi-Mao Hsu
  • Publication number: 20170076995
    Abstract: A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.
    Type: Application
    Filed: October 12, 2015
    Publication date: March 16, 2017
    Inventors: Yun-Tzu Chang, Shih-Min Chou, Kuo-Chih Lai, Ching-Yun Chang, Hsiang-Chieh Yen, Yen-Chen Chen, Yang-Ju Lu, Nien-Ting Ho, Chi-Mao Hsu
  • Patent number: 9576803
    Abstract: The present invention provides a method for metal gate work function tuning before contact formation in a fin-shaped field effect transistor (FinFET), where in the method comprises the following steps. (S1) providing a substrate having a metal gate structure on a side of the substrate, (S2) forming a titanium nitride (TiN) layer on the side of the substrate, and (S3) performing a gate annealing to tune work function of the metal gate structure.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: February 21, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kuo-Chih Lai, Yang-Ju Lu, Ching-Yun Chang, Yen-Chen Chen, Shih-Min Chou, Yun Tzu Chang, Fang-Yi Liu, Hsiang-Chieh Yen, Nien-Ting Ho
  • Publication number: 20160336181
    Abstract: The present invention provides a method for metal gate work function tuning before contact formation in a fin-shaped field effect transistor (FinFET), where in the method comprises the following steps. (S1) providing a substrate having a metal gate structure on a side of the substrate, (S2) forming a titanium nitride (TiN) layer on the side of the substrate, and (S3) performing a gate annealing to tune work function of the metal gate structure.
    Type: Application
    Filed: May 13, 2015
    Publication date: November 17, 2016
    Inventors: KUO-CHIH LAI, YANG-JU LU, CHING-YUN CHANG, YEN-CHEN CHEN, SHIH-MIN CHOU, YUN TZU CHANG, FANG-YI LIU, HSIANG-CHIEH YEN, NIEN-TING HO
  • Publication number: 20160327793
    Abstract: An autofocus head mounted display device is provided, including an imager and an eyeball tracker. The imager includes a display element, an optical element and a controller. An image light is projected to one of the eyeballs of the user by the display element. The convergence or divergence of the image light is adjusted by the optical element through the controller. The image is presented at an imaging position in front of the eyeballs of the user. The eyeball tracker is disposed at the position in front of the user's eyes. Both left eye and right eye rotational angles are detected simultaneously, so as to determine a focus position of the user's eyes. The eyeball tracker is connected to the controller. The optical element is adjusted by comparing the imaging position and the focus position, and the imaging position of the image is moved to the focus position.
    Type: Application
    Filed: February 1, 2016
    Publication date: November 10, 2016
    Inventors: YEN-CHEN CHEN, JINN-CHOU YOO, CHUN-MIN CHEN, CHENG-SHUN LIAO, SUNG-NAN CHEN
  • Patent number: 9478628
    Abstract: A metal gate forming process includes the following steps. A first metal layer is formed on a substrate by at least a first step followed by a second step, wherein the processing power of the second step is higher than the processing power of the first step.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: October 25, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Nien-Ting HO, Chi-Mao Hsu, Ching-Yun Chang, Yen-Chen Chen, Yang-Ju Lu, Shih-Min Chou, Yun-Tzu Chang, Hsiang-Chieh Yen, Min-Chuan Tsai
  • Publication number: 20150214035
    Abstract: Embodiments of a process for treating a fluid are provided. The process for treating a fluid includes supplying a first fluid to a circulating chamber and introducing a first gas to the first fluid. A portion of the first gas is dissolved in the first fluid and a portion of the first gas is held in a head space portion of the circulating chamber. The process further includes mixing a portion of the first fluid drawn out from the circulating chamber and a portion of the first gas drawn out from the head space portion to form a mixture. The process further includes spraying the mixture back into the circulating chamber by a two-fluid nozzle. In addition, the first gas is further dissolved into the first fluid to form a high conductivity fluid. The process further includes draining the high conductivity fluid from the circulating chamber.
    Type: Application
    Filed: January 24, 2014
    Publication date: July 30, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shing-Fong WU, Yung-Ti HUNG, Shih-Pao CHIEN, Yen-Chen CHEN
  • Patent number: 8982029
    Abstract: A pixel circuitry of a display device and a display method thereof are provided herein. The pixel circuitry includes a scan switch, a storage element, and a sampling circuitry. The scan switch has a first terminal coupled to a data line and configured to be asserted according to a scan signal. The storage element is coupled to a second terminal of the scan switch and configured to store a pixel voltage from the data line. The sampling circuitry is configured to sample the stored pixel voltage of the storage element and to obtain a reference voltage for the display device according to the sampled signal. By sampling the stored pixel voltage of the storage element, whether the pixel voltages with different polarities are symmetry can be detected for avoiding flickers.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: March 17, 2015
    Assignee: Himax Display, Inc.
    Inventors: Biing-Seng Wu, Hon-Yuan Leo, Cheng-Chi Yen, Yih-Long Tseng, Yung-Yuan Ho, Yen-Chen Chen
  • Publication number: 20150043216
    Abstract: A light emitting diode bulb includes a cover, a lighting module, a driving circuit module, a holder, and a conductive connector. The lighting module is arranged at one side of the cover and includes a plurality of light emitting diodes. The driving circuit module is arranged at the other side of the cover. The holder is assembled with the cover such that the lighting module is arranged between the holder and the cover. The conductive connector is assembled with the holder and opposite to the cover.
    Type: Application
    Filed: May 30, 2014
    Publication date: February 12, 2015
    Applicant: DELTA ELECTRONICS, INC.
    Inventors: Cheng-Hsiu DU, Kun-Yeuh LIN, Yen-Chen CHEN
  • Patent number: 8720062
    Abstract: A molding method for a thin-profile composite capillary structure includes the steps of preparing a metal grid and metal powder separately; attaching a liquid medium onto the metal grid by means of spraying or brushing or steeping; attaching uniformly the metal powder onto the grid with the liquid medium; and fixing the metal powder onto the surface of the grid by means of sintering, such that a sintered powder layer is formed onto the surface of the grid. The structure includes a metal grid, which is of planar grid pattern made of woven metal wires. A sintered powder layer is sintered onto a lateral surface of the metal grid from the metal powder. The thickness of the sintered powder layer is 0.1 mm-0.7 mm. The total thickness of the thin-profile composite capillary structure is 0.2 mm-0.8 mm, thus presenting flexibility. The thin-profile composite capillary structure is particularly suitable for a heat pipe.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: May 13, 2014
    Assignee: Forcecon Technology Co., Ltd.
    Inventors: Sin-Wei He, Jhong-Yan Chang, Yen-Chen Chen
  • Publication number: 20130174958
    Abstract: A molding method for a thin-profile composite capillary structure includes the steps of preparing a metal grid and metal powder separately; attaching a liquid medium onto the metal grid by means of spraying or brushing or steeping; attaching uniformly the metal powder onto the grid with the liquid medium; and fixing the metal powder onto the surface of the grid by means of sintering, such that a sintered powder layer is formed onto the surface of the grid. The structure includes a metal grid, which is of planar grid pattern made of woven metal wires. A sintered powder layer is sintered onto a lateral surface of the metal grid from the metal powder. The thickness of the sintered powder layer is 0.1 mm-0.7 mm. The total thickness of the thin-profile composite capillary structure is 0.2 mm-0.8 mm, thus presenting flexibility. The thin-profile composite capillary structure is particularly suitable for a heat pipe.
    Type: Application
    Filed: January 9, 2012
    Publication date: July 11, 2013
    Applicant: FORCECON TECHNOLOGY CO., LTD.
    Inventors: Sin-Wei He, Jhong - Yan Chang, Yen-Chen Chen