Abstract: An apparatus and a method for accessing a plurality of memory blocks is disclosed. The An apparatus comprises: a memory circuit configured to store a recording table, wherein the recording table corresponds to quality index of the plurality of memory blocks; and a control circuit configured to group the plurality of memory blocks to a first memory group and a second memory group according to the quality index; to enable to access the memory blocks in the first memory group, and to disable to access the memory blocks in the second memory group.

Abstract: An electronic device includes a flexible substrate and a peripheral trace. The flexible substrate includes an active region and a peripheral region situated outside of the active region. The flexible substrate includes a first bending part, a second bending part and a first cutting structure in the peripheral region. The first bending part is disposed on a first side region of the peripheral region and extending along a first direction. The second bending part is disposed on a second side region of the peripheral region and extending along a second direction not parallel to the first direction, and the second side region is adjacent to the first side region. The first cutting structure is adjacent to the first bending part and the second bending part. The peripheral trace is disposed on the flexible substrate and disposed between the active region and the first cutting structure.

Abstract: A manufacturing method of the flexible panel is provided. Firstly, a carrier substrate is provided. Then, an adhesion layer is formed on the carrier substrate, a flexible substrate is formed on the adhesion layer, and a buffer layer is formed on the flexible substrate. Then, a device layer is formed on the flexible substrate. Next, a separating process is performed for separating the flexible substrate and the device layer from the carrier substrate. According to a relation between a thermal expansion coefficient of the flexible substrate and a thermal expansion coefficient of the carrier substrate, the manufacturing method of the flexible panel selects a pattern of the adhesion layer. The pattern of the adhesion layer includes a frame adhesion structure or a plane adhesion structure.

Abstract: A computing system including a memory, a processor and a solid state disk is provided. The memory stores a disk access driver program. The solid state disk includes a storage circuit and a control circuit. The control circuit includes a processing unit, a first access path and a second access path. The processing unit communicates with the processor through the first access path. The processor executes the driver program that enables the processor to process a disk access command for directly accessing the storage circuit of the solid state disk through the second access path.

Abstract: An electrical device for a conveyance is provided. The electrical device includes a flexible display panel having a first edge and a partition device having a second edge. The partition device is disposed between the flexible display panel and the conveyance. A relative position between the first edge and the second edge is changeable.

Abstract: The present invention provides a flash memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the flash memory controller, the AI module receives data from a host device, and determines if the data is important data or unimportant data to generate a determination result. The microprocessor is configured to write the data into a flash memory module according to the determination result, wherein the flash memory module comprises a plurality of first blocks and a plurality of second blocks, and quantity of bits stored in each memory cell within the first blocks is lower than quantity of bits stored in each memory cell within the second blocks. When the determination result indicates that the data is the important data, the microprocessor only stores the data into at least one of the first blocks.

Abstract: A multi-axis hinge includes a first shaft, a first rotary member pivotally connected to the first shaft, a second shaft fixed to the first rotary member, a second rotary member pivotally connected to the second shaft, a first switching pin movably configured at the first rotary member, and a switching member fixed to the first shaft. The switching member includes a switching recess. When the first switching pin is located at the switching recess of the switching member, the second rotary member is rotatable relatively to the first rotary member. The second rotary member includes a switching recess. When the first switching pin is located at the switching recess of the second rotary member, the second rotary member is fixed to the first rotary member. An electronic device with the multi-axis hinge is also disclosed therein.

Abstract: The display device includes a first display panel and a second display panel. The first display panel includes first pixel structures having a first pixel pitch. The second display panel includes second pixel structures having a second pixel pitch. The first display panel is overlapped with the second display panel. A user would not see a moiré pattern generated by the display device by adjusting the first pixel pitch, the second pixel pitch, and an effective distance between the first display panel and the second display panel.

Abstract: The invention provides a touch display apparatus including a display device, a polarizer device, and a touch device. The polarizer device and the touch device are stacked on the display device. The touch device has a substrate with a thickness-direction phase retardation value Rth, and 0 nm?|Rth|?100 nm. The touch display apparatus has high display quality under the irradiation of an ambient beam.

Abstract: A power quality detecting system includes a power module, a storage device, and a power quality detecting module. The power module receives an external power source. The power module converts the external power source into a first internal voltage. The power quality detecting module is electrically connected to the power module and the storage device. The storage device is electrically connected to the power module for receiving the first internal voltage through the power quality detecting module. The power quality detecting module determines whether a first alarm signal is transmitted according to a quality parameter of the first internal voltage.

Abstract: A memory device includes a data calculation circuit, a space calculation circuit, and a warning circuit. The data calculation circuit is coupled to a memory, and is configured to determine a data quantity of valid data stored in the memory. The space calculation circuit is coupled to the memory, and is configured to determine a data capacity of a current valid storage space of the memory. The warning circuit is configured to determine a threshold capacity according to the data quantity, and is configured to determine whether to output a warning message according to the data capacity, the data quantity, and the threshold capacity.

Abstract: The present invention provides a flash memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the flash memory controller, the AI module receives data from a host device, and determines if the data is important data or unimportant data to generate a determination result. The microprocessor is configured to write the data into a flash memory module according to the determination result, wherein the flash memory module comprises a plurality of first blocks and a plurality of second blocks, and quantity of bits stored in each memory cell within the first blocks is lower than quantity of bits stored in each memory cell within the second blocks. When the determination result indicates that the data is the important data, the microprocessor only stores the data into at least one of the first blocks.

Abstract: The present invention provides a flash memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the flash memory controller, the AI module receives data from a host device, and determines if the data is hot data or cold data to generate a determination result. The microprocessor is configured to selectively write the data into a first block or a second block within a flash memory module according to the determination result, wherein quantity of bits stored in each memory cell within the first block is different from quantity of bits stored in each memory cell within the second block.

Abstract: The present invention provides a memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the memory controller, the AI module receives a read command from a host device, and generates an auxiliary read command according to the read command. The microprocessor reads first data from a memory module according to the read command, and reads second data from the memory module according to the auxiliary read command, wherein a logical address the second data is not recorded in the read command.

Abstract: The present invention provides a memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the memory controller, the AI module receives a read command from a host device, and generates an auxiliary command according to the read command. The microprocessor is configured to select a first L2P mapping table according to a logical address included in the read command, and refer to the first L2P mapping table to read data from a memory module. The microprocessor is further configured to read a second L2P mapping table from the memory module according to the auxiliary command, wherein the second L2P mapping table does not include the logical address included in the read command.

Abstract: The present invention provides a memory controller including an artificial intelligence (AI) module and a microprocessor. In the operations of the memory controller, the AI module is arranged to determine a first user behavior model or a second user behavior model to generate a determination result according to a plurality of access commands and/or a plurality of parameters of a memory module controlled by the memory module. When the determination result indicates the first user behavior model, the microprocessor uses a first control strategy to control the memory module; and when the determination result indicates the second user behavior model, the microprocessor uses a second control strategy different from the first control strategy to control the memory module.

Abstract: An amplifier circuitry includes a current source circuit, a voltage regulator circuit, and an amplifier. The current source circuit generates a first bias current. The voltage regulator circuit regulates a reference voltage to generate a supply voltage. The voltage regulator circuit includes a first and a second compensation resistors, the first and the second compensation resistors are configured to generate the reference voltage according to a reference a second bias currents, and a first ratio is present between the first and the second biasing currents. The amplifier includes first load resistors which are configured to generate a first common-mode output signal based on the supply voltage and the first bias current. The second ratio is present between the second compensation resistor and one of the first load resistors, and the first and the second ratios are arranged to compensate the first common-mode output signal.

Abstract: An amplifier circuitry includes a current source circuit, a voltage regulator circuit, and an amplifier. The current source circuit generates a first bias current. The voltage regulator circuit regulates a reference voltage to generate a supply voltage. The voltage regulator circuit includes a first and a second compensation resistors, the first and the second compensation resistors are configured to generate the reference voltage according to a reference a second bias currents, and a first ratio is present between the first and the second biasing currents. The amplifier includes first load resistors which are configured to generate a first common-mode output signal based on the supply voltage and the first bias current. The second ratio is present between the second compensation resistor and one of the first load resistors, and the first and the second ratios are arranged to compensate the first common-mode output signal.

Abstract: A clock and data recovery device includes a data analysis circuit, a loop filter circuit, and a phase adjust circuit. The data analysis circuit is configured to generate an error signal according to input data, a first clock signal, and a second clock signal. The loop filter circuit is configured to generate an adjust signal according to the error signal. A phase filter circuit is configured to generate a first control signal according to the error signal. A switching element of a first frequency filter circuit is configured to output a second control signal according to the error signal and a first switching signal that has a first period. A first adder is configured to generate the adjust signal according to the first control signal and the second control signal. The phase adjust circuit is configured to adjust the first clock signal and the second clock signal.

Abstract: A multi-channel transceiver includes a phase-locked loop circuit, a first transmitting channel and a second transmitting channel. The phase-locked loop circuit generates a first clock signal set and a second clock signal set with different frequencies. The first transmitting channel includes a first phase adjusting circuit and a first transmitter. The first phase adjusting circuit receives the first clock signal set and generates a first spread spectrum clock signal with a first SSCG profile. According to the first spread spectrum clock signal, the first transmitter generates a first serial data. The second transmitting channel includes a second phase adjusting circuit and a second transmitter. The second phase adjusting circuit receives the second clock signal set and generates a second spread spectrum clock signal with a second SSCG profile. According to the second spread spectrum clock signal, the second transmitter generates a second serial data.