Abstract: A hinge component for an electronic device includes a fixing member, a rotating member and a central shaft. The fixing member includes a side plate and two fixing plates, a curved guiding rail is formed on the side plate. The rotating member includes a rotating portion, a connecting portion and an engaging portion. The fixing member and the rotating member are assembled to the casing and the back plate of the electronic device. The fixing member is disposed inside the casing but not exposed. As a result, the electronic device is made thinner. The hinge component is not easily damaged under an external force, and the lifecycle of the hinge component is improved. The rotating portion rotates around the connection of the back plate and the casing as a virtual rotating axis. At the same time, the central shaft is driven to slide in the curved guiding rail.

Abstract: A method of inhibiting an irregular aggregation of a nanosized powder includes (A) providing a nanosized ceramic powder to perform thereon a thermal analysis and thereby attain an endothermic peak temperature; (B) performing an impurity-removal heat treatment on the nanosized ceramic powder at a temperature higher than the endothermic peak temperature; (C) switching the nanosized ceramic powder from a temperature environment of the impurity-removal heat treatment to an environment of a temperature higher than a phase change temperature of the nanosized ceramic powder, followed by performing a calcination heat treatment on the nanosized ceramic powder in the environment of the temperature higher than the phase change temperature of the nanosized ceramic powder, wherein the nanosized ceramic powder skips the temperature environment between impurity-removal heat treatment and calcination heat treatment to shun generating a vermicular structure, avoid crystalline irregularity and abnormal growth, reduce particle

Abstract: A clock and data recovery device includes a data sampling module, a phase detection circuit, a frequency estimator, a clock generation module, and a data recovery module. The data sampling module samples input data according to first clock signals to generate data values, in which phases of the first clock signals are different from one another. The phase detection circuit detects a phase error of the input data according to at least one second clock signal, to generate an error signal. The frequency estimator generates an adjustment signal according to the error signal, a phase threshold value, and a frequency threshold value. The clock generation module generates the first clock signals and the at least one second clock signal according to the adjustment signal and a reference clock signal. The data recovery module generates recovered data corresponding to the input data according to the data values.

Abstract: A clock and data recovery device includes a data sampling module, a phase detection circuit, a frequency estimator, a clock generation module, and a data recovery module. The data sampling module samples input data according to first clock signals to generate data values, in which phases of the first clock signals are different from one another. The phase detection circuit detects a phase error of the input data according to at least one second clock signal, to generate an error signal. The frequency estimator generates an adjustment signal according to the error signal, a phase threshold value, and a frequency threshold value. The clock generation module generates the first clock signals and the at least one second clock signal according to the adjustment signal and a reference clock signal. The data recovery module generates recovered data corresponding to the input data according to the data values.

Abstract: A hinge assembly adapted to an electronic device is provided. The hinge assembly comprises a fixing member, a sliding shaft, a connecting member, a rotating shaft and a rotating member. A curved guide rail is formed at the side plate. When the sliding shaft is located at a first position and a force applies on the rotating member, the sliding shaft moves from the first position to a second position along the curved guide rail, when the sliding shaft is located at the second position of the curved guide rail and the force applies on the rotating member continuously, the rotating member rotates around the rotating shaft.

Abstract: A hinge component for an electronic device includes a fixing member, a rotating member and a central shaft. The fixing member includes a side plate and two fixing plates, a curved guiding rail is formed on the side plate. The rotating member includes a rotating portion, a connecting portion and an engaging portion. The fixing member and the rotating member are assembled to the casing and the back plate of the electronic device. The fixing member is disposed inside the casing but not exposed. As a result, the electronic device is made thinner. The hinge component is not easily damaged under an external force, and the lifecycle of the hinge component is improved. The rotating portion rotates around the connection of the back plate and the casing as a virtual rotating axis. At the same time, the central shaft is driven to slide in the curved guiding rail.

Abstract: A SSD controlling circuit includes: a read and write circuit for coupling with a SSD; and a flash memory controlling circuit coupled with the read and write circuit and configured to operably conduct following operations: reading data from a target data block of the SSD and conduct error checking and correction operation on retrieved data; if uncorrectable error occurs, moving data of the target data block to other blocks; erasing the target data block; writing test data into the target data block; after a predetermined time, reading test data from the target data block and conduct error checking and correction operation on retrieved data; recording error counts of the target data block; and determining the reusability of the target data block according to the recorded error counts.

Abstract: A memory device includes a memory module and a control module. The control module is coupled to the memory module and is configured to store data into the memory module according to a first mapping table. The control module includes a storing unit and a guaranteeing unit. The storing unit is configured to store the first mapping table. The guaranteeing unit is coupled to the storing unit and is configured to determine whether the first mapping table is correct or not. The guaranteeing unit is further configured to issue an error signal in a state where the first mapping table is incorrect.

Abstract: The present disclosure provides a weighting-type data relocation control device for controlling data relocation of a non-volatile memory which includes used blocks and unused blocks. Each used block is associated with a first parameter and a second parameter. The control device executes the following steps: multiplying the first and second parameters by a first and a second weightings respectively to obtain a priority index, in which at least one of the parameters and/or at least one of the weightings relate(s) to a thermal detection result; comparing the priority index with at least a threshold to obtain a comparison result; and if the comparison result corresponding to a used storage block of the used blocks reaches a predetermined threshold, transferring valid data of the used storage block to one of the unused blocks.

Abstract: A latch circuit including a symmetric circuit, a clock receiving circuit, a current generating circuit, a sampling circuit and a holding circuit is provided. The clock receiving circuit receives a first clock signal and a second clock signal. A phase difference between the first clock signal and the second clock signal is 180 degrees. The current generating circuit is electrically connected with the symmetric circuit and the clock receiving circuit, for providing a discharge current. The sampling circuit is electrically connected with the current generating circuit. According to the first clock signal, the sampling circuit receives a differential input signal, and the discharge current flows through the sampling circuit. The holding circuit is electrically connected with the current generating circuit. According to the second clock signal, the discharge current flows through the holding circuit, and the holding circuit generates a differential output signal.

Abstract: A method for making an electromagnetic wave shielding material comprises the steps of (a) mixing ternary Fe—Al—Si alloy powders and a solvent to prepare a Fe—Al—Si solution; (b) adding an acid in the Fe—Al—Si solution to release Fe ions through a dissolution reaction; (c) adding copper chloride powders in the Fe—Al—Si solution; (d) adding a lye in the Fe—Al—Si solution to induce a displacement reaction; (e) adding a silane coupling agent in the Fe—Al—Si solution; (f) placing the Fe—Al—Si solution in a microwave reactor to accelerate the displacement reaction; (g) producing a quaternary Cu—Fe—Al—Si alloy after the displacement reaction of the Fe—Al—Si solution, thereby forming a quaternary Cu—Fe—Al—Si alloy solution, which proceeding with a solid-liquid separation and a drying treatment to obtain an electromagnetic wave shielding material composed of quaternary Cu—Fe—Al—Si alloy in solid powders.

Abstract: A clock and data recovery (CDR) circuit is provided, and includes a sampling module, an error sampler, a phase detect module, and a phase adjust module. The sampling module generates a data signal according to an input data and a first clock signal, and generates an edge signal according to the input data and a second clock signal. The error sampler compares the input data with a reference voltage according to the first clock signal to generate a control signal. The phase detect module receives the control signal and generates a corrective signal according to the data signal and the edge signal. When the values of the control signal and the data signal are different, the phase detect module stops transmitting the corrective signal. The phase adjust module generates and adjusts the first and the second clock signal according to the corrective signal.

Abstract: A multi-channel transceiver includes a phase-locked loop circuit, a first transmitting channel and a second transmitting channel. The phase-locked loop circuit generates a first clock signal set and a second clock signal set with different frequencies. The first transmitting channel includes a first phase adjusting circuit and a first transmitter. The first phase adjusting circuit receives the first clock signal set and generates a first spread spectrum clock signal with a first SSCG profile. According to the first spread spectrum clock signal, the first transmitter generates a first serial data. The second transmitting channel includes a second phase adjusting circuit and a second transmitter. The second phase adjusting circuit receives the second clock signal set and generates a second spread spectrum clock signal with a second SSCG profile. According to the second spread spectrum clock signal, the second transmitter generates a second serial data.

Abstract: An active inductor includes a first transistor, a capacitor, a second transistor, a first resistor, a second resistor, and a bias current source. A source terminal of the first transistor is a first terminal of the active inductor and connected to a first voltage source. The capacitor is connected to the source terminal and gate terminal of the first transistor. A drain terminal of the second transistor is connected to the source terminal of the first transistor. A gate terminal of the second transistor is connected to a drain terminal of the first transistor. The first resistor is connected between the drain terminal of the first transistor and a second terminal of the active inductor. The second resistor is connected to a source terminal of the second transistor. The bias current source is connected between the second resistor and a second voltage source.

Abstract: A clock and data recovery (CDR) circuit and method are disclosed herein. The CDR circuit includes a data analysis module, a loop filter module and a phase adjust module. The data analysis module generates an error signal according to an input data, a first clock signal, and a second clock signal. The loop filter module generates a first corrective signal according to the error signal, a frequency threshold value, and a phase threshold value. The phase adjust module generates the first clock signal and the second clock signal according to the first corrective signal. The loop filter module further accumulates the error signal to generate an accumulated value, and to compare the accumulated value with an accumulated threshold value, so as to dynamically adjust the accumulated threshold value, the frequency threshold value, and the phase threshold value.

Abstract: An eye diagram measuring circuit includes a reference signal generator, a clock data recovery circuit, a test signal generator, and a boundary determining unit. The reference signal generator generates a reference signal. The clock data recovery circuit generates a clock signal according to the reference signal. The test signal generator generates a first sampling signal according to the clock signal. The test signal generator discriminates logic levels of plural bits of the input signal according to the first sampling signal and a slicing voltage, thereby generating a test signal. The boundary determining unit generates a boundary of an eye diagram according to a relationship between the test signal and the reference signal. The test signal generator changes a phase of the first sampling signal and a magnitude of the slicing voltage according to plural conditions provided by the boundary determining unit.

Abstract: A solid state drive includes a flash memory, a cache memory, and a controlling unit. The solid state drive is in communication with a host. The flash memory includes a plurality of blocks, wherein each of the blocks has a plurality of pages. The cache memory includes a plurality of cache units. The cache units are allocated into a plurality of groups according to operating statuses of respective cache units. The controlling unit is in communication with the host, the flash memory and the cache memory. Under control of the controlling unit, a write data from the host is temporarily stored in the cache memory so as to be written into the flash memory, or a read data from the flash memory is temporarily stored in the cache memory so as to be provided to the host.

Abstract: ESD clamp circuit is provided, including an RC circuit, a first transistor, a second transistor, an ESD conduction unit and an inverter. The first transistor has a gate and a drain respectively coupled to the RC circuit and a control terminal of the ESD conduction unit. The inverter has an input terminal coupled to the control terminal. The second transistor has a drain and a gate respectively coupled to the control terminal and an output terminal of the inverter. The gates of the first and second transistors are isolated; also the output terminal and the gate of the first transistor are isolated.

Abstract: A current-mode D latch includes a first load element, a second load element, a first bias current source, a first switch transistor, a second switch transistor, a first stage circuit and a second stage circuit. The first switch transistor is controlled by an inverted reset signal. The second switch transistor is controlled by a reset signal. When an inverted clock signal is in a first level state and the reset signal is inactive, the first input signal is converted into the first output signal and the first inverted input signal is converted into the first inverted output signal by the first stage circuit. When a clock signal is in the first level state and the reset signal is inactive, the first output signal and the first inverted output signal are maintained by the second stage circuit.

Abstract: Eye diagram scan circuit and associated method for a receiver circuit, including a level adjust circuit, a phase interpolator and a control module. The receiver circuit provides a first data signal and a primary phase data according to a received signal. The control module provides a phase offset data and a level offset data. The level adjust circuit adjusts a level of the received signal in respond to the level offset data; the phase interpolator triggers according to a sum of the phase offset data and the primary phase data, so a second data signal is provide in response to the level-adjusted received signal. The control module compares the first data signal and the second data signal, and accordingly provides an eye diagram scan result for the phase offset data and the level offset data.