Patents by Inventor Yen-Jen Chen
Yen-Jen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210341535Abstract: A test circuit includes an oscillator configured to generate an oscillation signal, a device-under-test (DUT) configured to output an AC signal based on the oscillation signal, a first detection circuit configured to generate a first DC voltage having a first value based on the oscillation signal, and a second detection circuit configured to generate a second DC voltage having a second value based on the AC signal.Type: ApplicationFiled: July 15, 2021Publication date: November 4, 2021Inventors: Hsieh-Hung HSIEH, Yen-Jen CHEN, Tzu-Jin YEH
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Patent number: 11079428Abstract: A test circuit includes an amplifier configured to receive an AC signal, and output an amplified AC signal based on the AC signal, a first detection circuit configured to generate a first DC voltage having a first value based on an amplitude of the AC signal, and a second detection circuit configured to generate a second DC voltage having a second value based on an amplitude of the amplified AC signal.Type: GrantFiled: April 10, 2020Date of Patent: August 3, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsieh-Hung Hsieh, Yen-Jen Chen, Tzu-Jin Yeh
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Publication number: 20210181251Abstract: A test circuit includes an amplifier configured to receive an AC signal, and output an amplified AC signal based on the AC signal, a first detection circuit configured to generate a first DC voltage having a first value based on an amplitude of the AC signal, and a second detection circuit configured to generate a second DC voltage having a second value based on an amplitude of the amplified AC signal.Type: ApplicationFiled: April 10, 2020Publication date: June 17, 2021Inventors: Hsieh-Hung HSIEH, Yen-Jen CHEN, Tzu-Jin YEH
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Publication number: 20210132158Abstract: A testing system includes: a signal generator arranged to generate a testing signal; a dividing circuit coupled to the signal generator for providing a plurality of input signals according to the testing signal; and a plurality of power-amplifier chips coupled to the dividing circuit for being tested by generating a plurality of output signals for a predetermined testing time according to the plurality of input signals respectively.Type: ApplicationFiled: October 30, 2019Publication date: May 6, 2021Inventors: HSIEH-HUNG HSIEH, WU-CHEN LIN, YEN-JEN CHEN, TZU-JIN YEH
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Patent number: 10192833Abstract: Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.Type: GrantFiled: November 17, 2015Date of Patent: January 29, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Feng-Wei Kuo, Hui Yu Lee, Huan-Neng Chen, Yen-Jen Chen, Yu-Ling Lin, Chewn-Pu Jou
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Patent number: 10148216Abstract: A package of a supporting device for photovoltaic panels includes a container and components, for forming the supporting device, packed in the container. The components include at least two frame supports, of which at least one is provided with an inverter attached thereon in advance. Thereby, a user can quickly assemble the supporting device. Furthermore, the inverter is substantially positioned in the container, which is conducive to stabilization in the weight distribution of the components in the container and facilitates the transport of the package. In addition, a kit for forming a supporting device for at least one photovoltaic panel includes components for forming the supporting device. The kit can be provided without a container for accommodating the components. Similarly, the components include at least two frame supports, of which at least one is provided with an inverter attached thereon in advance, which facilitates the assembly of the supporting device.Type: GrantFiled: June 11, 2015Date of Patent: December 4, 2018Assignee: DARFON ELECTRONICS CORP.Inventors: Frank O'Young, Yen-Jen Chen
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Patent number: 9838024Abstract: A method of generating an output signal includes determining a sampling period N according to a number of most significant bits (MSBs) of a divider number control signal. The method also includes determining a first logic value of a control signal by a comparing circuit based on the sampling period N, and generating a coarse tuning signal by a code generating circuit based on a phase difference signal and the control signal. When an M-th least significant bit (LSB) of the number of MSBs of the divider number control signal equals a second logic value, the sampling period N is set based on the M-th LSB of the number of MSBs of the divider number control signal.Type: GrantFiled: November 2, 2016Date of Patent: December 5, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Jen Chen, Feng Wei Kuo, Huan-Neng Chen, Chewn-Pu Jou
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Patent number: 9705466Abstract: A semiconductor device comprises a guarded circuit. The semiconductor device also comprises a guard ring surrounding the guarded circuit. The semiconductor device further comprises a resonant circuit coupled with the guard ring. The resonant circuit comprises an input node coupled with the guard ring. The resonant circuit also comprises an inductor. The resonant circuit further comprises a capacitor coupled with the inductor. The resonant circuit additionally comprises a ground node configured to carry a ground voltage. The inductor and the capacitor are coupled between the input node and the ground node.Type: GrantFiled: February 25, 2015Date of Patent: July 11, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Jen Chen, Chi-Feng Huang, Hsiao-Chun Lee, Hsieh-Hung Hsieh, Tzu-Jin Yeh
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Publication number: 20170077932Abstract: A method of generating an output signal includes determining a sampling period N according to a number of most significant bits (MSBs) of a divider number control signal. The method also includes determining a first logic value of a control signal by a comparing circuit based on the sampling period N, and generating a coarse tuning signal by a code generating circuit based on a phase difference signal and the control signal. When an M-th least significant bit (LSB) of the number of MSBs of the divider number control signal equals a second logic value, the sampling period N is set based on the M-th LSB of the number of MSBs of the divider number control signal.Type: ApplicationFiled: November 2, 2016Publication date: March 16, 2017Inventors: Yen-Jen CHEN, Feng Wei KUO, Huan-Neng CHEN, Chewn-Pu JOU
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Publication number: 20160365824Abstract: A package of a supporting device for photovoltaic panels includes a container and components, for forming the supporting device, packed in the container. The components include at least two frame supports, of which at least one is provided with an inverter attached thereon in advance. Thereby, a user can quickly assemble the supporting device. Furthermore, the inverter is substantially positioned in the container, which is conducive to stabilization in the weight distribution of the components in the container and facilitates the transport of the package. In addition, a kit for forming a supporting device for at least one photovoltaic panel includes components for forming the supporting device. The kit can be provided without a container for accommodating the components. Similarly, the components include at least two frame supports, of which at least one is provided with an inverter attached thereon in advance, which facilitates the assembly of the supporting device.Type: ApplicationFiled: June 11, 2015Publication date: December 15, 2016Inventors: Frank O'Young, Yen-Jen Chen
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Patent number: 9490819Abstract: An apparatus comprises a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal. The apparatus also comprises a digital loop filter configured to generate a fine tuning signal based on the phase difference signal. The apparatus further comprises a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal. The apparatus additionally comprises a divider configured to generate a divider frequency based on a divider control signal and the output signal. The phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal.Type: GrantFiled: January 23, 2015Date of Patent: November 8, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Jen Chen, Feng Wei Kuo, Huan-Neng Chen, Chewn-Pu Jou
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Patent number: 9432030Abstract: A phase locked loop (PLL) includes a voltage controlled oscillator (VCO), a loop filter, and a feedback control unit. The VCO is configured to generate a first oscillating signal and a second oscillating signal according to a VCO control signal. The loop filter is configured to output the VCO control signal by low-pass filtering a signal at an input node of the loop filter. The feedback control unit has an output node coupled to the input node of the loop filter, the feedback control unit is configured to apply a first predetermined amount of current, along a first current direction, to the first feedback control output node during a variable period of time; and to apply one of K second predetermined amounts of current, along a second current direction opposite the first current direction, to the first feedback control output node during a predetermined period of time.Type: GrantFiled: December 5, 2013Date of Patent: August 30, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Jen Chen, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh
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Publication number: 20160248394Abstract: A semiconductor device comprises a guarded circuit. The semiconductor device also comprises a guard ring surrounding the guarded circuit. The semiconductor device further comprises a resonant circuit coupled with the guard ring. The resonant circuit comprises an input node coupled with the guard ring. The resonant circuit also comprises an inductor. The resonant circuit further comprises a capacitor coupled with the inductor. The resonant circuit additionally comprises a ground node configured to carry a ground voltage. The inductor and the capacitor are coupled between the input node and the ground node.Type: ApplicationFiled: February 25, 2015Publication date: August 25, 2016Inventors: Yen-Jen CHEN, Chi-Feng HUANG, Hsiao-Chun LEE, Hsieh-Hung HSIEH, Tzu-Jin YEH
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Patent number: 9374038Abstract: A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.Type: GrantFiled: December 19, 2013Date of Patent: June 21, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Jen Chen, I-Ting Lee, Feng Wei Kuo, Huan-Neng Chen, Chewn-Pu Jou
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Publication number: 20160071805Abstract: Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.Type: ApplicationFiled: November 17, 2015Publication date: March 10, 2016Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Feng-Wei KUO, Hui Yu LEE, Huan-Neng CHEN, Yen-Jen CHEN, Yu-Ling LIN, Chewn-Pu JOU
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Patent number: 9219039Abstract: Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.Type: GrantFiled: September 5, 2013Date of Patent: December 22, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Feng-Wei Kuo, Hui Yu Lee, Huan-Neng Chen, Yen-Jen Chen, Yu-Ling Lin, Chewn-Pu Jou
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Patent number: 9176479Abstract: A time-to-digital converter (TDC) comprises a first delay line including a plurality of first delay cells connected in series, wherein each of the first delay cells include a plurality of first delay units connected in series, wherein each of the first delay units includes a tunable PMOS transistor, a first poly on oxide definition (OD) edge (PODE) transistor, and a pull-up PMOS transistor. The TDC further comprises a second delay line including a plurality of second delay cells connected in series, wherein each of the second delay cells include a plurality of second delay units connected in series, wherein each of the second delay units includes a tunable NMOS transistor, a second PODE transistor, and a pull-down NMOS transistor.Type: GrantFiled: January 23, 2014Date of Patent: November 3, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsieh-Hung Hsieh, Yen-Jen Chen, Chewn-Pu Jou
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Publication number: 20150205267Abstract: A time-to-digital converter (TDC) comprises a first delay line including a plurality of first delay cells connected in series, wherein each of the first delay cells include a plurality of first delay units connected in series, wherein each of the first delay units includes a tunable PMOS transistor, a first poly on oxide definition (OD) edge (PODE) transistor, and a pull-up PMOS transistor. The TDC further comprises a second delay line including a plurality of second delay cells connected in series, wherein each of the second delay cells include a plurality of second delay units connected in series, wherein each of the second delay units includes a tunable NMOS transistor, a second PODE transistor, and a pull-down NMOS transistor.Type: ApplicationFiled: January 23, 2014Publication date: July 23, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsieh-Hung Hsieh, Yen-Jen Chen, Chewn-Pu Jou
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Publication number: 20150162921Abstract: A phase locked loop (PLL) includes a voltage controlled oscillator (VCO), a loop filter, and a feedback control unit. The VCO is configured to generate a first oscillating signal and a second oscillating signal according to a VCO control signal. The loop filter is configured to output the VCO control signal by low-pass filtering a signal at an input node of the loop filter. The feedback control unit has an output node coupled to the input node of the loop filter, the feedback control unit is configured to apply a first predetermined amount of current, along a first current direction, to the first feedback control output node during a variable period of time; and to apply one of K second predetermined amounts of current, along a second current direction opposite the first current direction, to the first feedback control output node during a predetermined period of time.Type: ApplicationFiled: December 5, 2013Publication date: June 11, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Jen CHEN, Hsieh-Hung HSIEH, Chewn-Pu JOU, Fu-Lung HSUEH
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Publication number: 20150130518Abstract: An apparatus comprises a code generator configured to generate a coarse tuning signal and a reset signal based on a reference frequency and a phase difference signal. The apparatus also comprises a digital loop filter configured to generate a fine tuning signal based on the phase difference signal. The apparatus further comprises a voltage control oscillator configured to generate an output signal based on the coarse tuning signal and the fine tuning signal. The apparatus additionally comprises a divider configured to generate a divider frequency based on a divider control signal and the output signal. The phase difference signal is based, at least in part, on the divider frequency, and the divider is configured to be reset based on the reset signal.Type: ApplicationFiled: January 23, 2015Publication date: May 14, 2015Inventors: Yen-Jen CHEN, Feng Wei KUO, Huan-Neng CHEN, Chewn-Pu JOU