Patents by Inventor Yen-Jen Chen
Yen-Jen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8963595Abstract: A shared loop filter includes an input port configured to selectively receive a first input from a first charge pump. The first charge pump is connected to a first phase locked loop (PLL) in a first die. The input port is further configured to selectively receive a second input from a second charge pump, the second charge pump connected to a second PLL in a second die separate from the first die. The shared loop filter further includes an output port configured to selectively provide an output to a first voltage controlled oscillator (VCO). The first VCO is connected to the first PLL. The output port is further configured to selectively output a second output to a second VCO. The second VCO is connected to the second PLL.Type: GrantFiled: July 28, 2014Date of Patent: February 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Wei Kuo, Shyh-An Chi, Huan-Neng Chen, Yen-Jen Chen, Chewn-Pu Jou
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Patent number: 8953730Abstract: A phase locked loop includes a phase difference detector configured to receive a reference frequency and a divider frequency and output a phase difference signal. The phase locked loop includes a code generator configured to receive the reference frequency and the phase difference signal, and output a coarse tuning signal and a reset signal. The phase locked loop includes a digital loop filter configured to receive the phase difference signal and output a fine tuning signal. The phase locked loop includes a voltage control oscillator configured to receive the coarse and fine tuning signals, and output an output frequency. The phase locked loop includes a divider configured to receive the reset signal, a divider number control signal and the output frequency, and output the divider frequency. The phase locked loop includes a delta-sigma modulator configured to receive a divisor ratio and the reset signal, and output divider number control signal.Type: GrantFiled: April 20, 2012Date of Patent: February 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Jen Chen, Feng Wei Kuo, Huan-Neng Chen, Chewn-Pu Jou
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Patent number: 8890626Abstract: One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.Type: GrantFiled: August 15, 2012Date of Patent: November 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yen-Jen Chen, I-Ting Lee, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh, Shen-Iuan Liu
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Publication number: 20140333355Abstract: A shared loop filter includes an input port configured to selectively receive a first input from a first charge pump. The first charge pump is connected to a first phase locked loop (PLL) in a first die. The input port is further configured to selectively receive a second input from a second charge pump, the second charge pump connected to a second PLL in a second die separate from the first die. The shared loop filter further includes an output port configured to selectively provide an output to a first voltage controlled oscillator (VCO). The first VCO is connected to the first PLL. The output port is further configured to selectively output a second output to a second VCO. The second VCO is connected to the second PLL.Type: ApplicationFiled: July 28, 2014Publication date: November 13, 2014Inventors: Feng Wei KUO, Shyh-An CHI, Huan-Neng CHEN, Yen-Jen CHEN, Chewn-Pu JOU
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Patent number: 8836390Abstract: An integrated circuit die stack includes a first die having a first phase locked loop (PLL) and a second die having a second PLL. The first PLL includes a first voltage controlled oscillator (VCO) and the second PLL includes a second VCO. The first VCCO and the second VCCO share a frequency divider and a loop filter.Type: GrantFiled: September 27, 2013Date of Patent: September 16, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Wei Kuo, Shyh-An Chi, Huan-Neng Chen, Yen-Jen Chen, Chewn-Pu Jou
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Patent number: 8816731Abstract: An integrated circuit includes a first die and a second die. The first die comprising a first phase-locked loop (PLL) and the second die comprising a second PLL. The integrated circuit includes a shared loop filter, wherein the first PLL in the first die is combined with the shared loop filter to form a first PLL feedback loop, the second PLL in the second die is combined with the shared loop filter to form a second PLL feedback loop and the shared loop filter is configured to provide configurable bandwidths to each of the first PLL feedback loop and the second PLL feedback loop.Type: GrantFiled: September 12, 2013Date of Patent: August 26, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Wei Kuo, Shyh-An Chi, Huan-Neng Chen, Yen-Jen Chen, Chewn-Pu Jou
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Publication number: 20140103961Abstract: A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.Type: ApplicationFiled: December 19, 2013Publication date: April 17, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Jen CHEN, I-Ting LEE, Feng Wei KUO, Huan-Neng CHEN, Chewn-Pu JOU
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Publication number: 20140049329Abstract: One or more techniques and systems for a divider-less phase locked loop (PLL) and associated phase detector (PD) are provided herein. In some embodiments, a pulse phase detector (pulsePD) signal, a voltage controlled oscillator positive differential (VCOP) signal, and a voltage controlled oscillator negative differential (VCON) signal are received. An up signal and a down signal for a first charge pump (CP) and an up signal and a down signal for a second CP are generated based on the pulsePD signal, the VCOP signal, and the VCON signal. For example, CP signals are generated to control the first CP and the second CP, respectively. In some embodiments, CP signals are generated such that the CPs facilitate adjustment of a zero crossing phase of the VCON and VCOP signals with respect to the pulsePD signal. In this manner, a divider-less PLL is provided, thus mitigating PLL power consumption.Type: ApplicationFiled: August 15, 2012Publication date: February 20, 2014Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yen-Jen Chen, I-Ting Lee, Hsieh-Hung Hsieh, Chewn-Pu Jou, Fu-Lung Hsueh, Shen-Luan Liu
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Patent number: 8643402Abstract: A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.Type: GrantFiled: November 30, 2011Date of Patent: February 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Jen Chen, I-Ting Lee, Feng Wei Kuo, Huan-Neng Chen, Chewn-Pu Jou
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Publication number: 20140021989Abstract: An integrated circuit die stack includes a first die having a first phase locked loop (PLL) and a second die having a second PLL. The first PLL includes a first voltage controlled oscillator (VCO) and the second PLL includes a second VCO. The first VCCO and the second VCCO share a frequency divider and a loop filter.Type: ApplicationFiled: September 27, 2013Publication date: January 23, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng Wei KUO, Shyh-An CHI, Huan-Neng CHEN, Yen-Jen CHEN, Chewn-Pu JOU
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Publication number: 20140015576Abstract: An integrated circuit includes a first die and a second die. The first die comprising a first phase-locked loop (PLL) and the second die comprising a second PLL. The integrated circuit includes a shared loop filter, wherein the first PLL in the first die is combined with the shared loop filter to form a first PLL feedback loop, the second PLL in the second die is combined with the shared loop filter to form a second PLL feedback loop and the shared loop filter is configured to provide configurable bandwidths to each of the first PLL feedback loop and the second PLL feedback loop.Type: ApplicationFiled: September 12, 2013Publication date: January 16, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng Wei KUO, Shyh-An CHI, Huan-Neng CHEN, Yen-Jen CHEN, Chewn-Pu JOU
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Publication number: 20140001609Abstract: Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.Type: ApplicationFiled: September 5, 2013Publication date: January 2, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Feng-Wei KUO, Hui Yu LEE, Huan-Neng CHEN, Yen-Jen CHEN, Yu-Ling LIN, Chewn-Pu JOU
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Publication number: 20130278303Abstract: A phase locked loop includes a phase difference detector configured to receive a reference frequency and a divider frequency and output a phase difference signal. The phase locked loop includes a code generator configured to receive the reference frequency and the phase difference signal, and output a coarse tuning signal and a reset signal. The phase locked loop includes a digital loop filter configured to receive the phase difference signal and output a fine tuning signal. The phase locked loop includes a voltage control oscillator configured to receive the coarse and fine tuning signals, and output an output frequency. The phase locked loop includes a divider configured to receive the reset signal, a divider number control signal and the output frequency, and output the divider frequency. The phase locked loop includes a delta-sigma modulator configured to receive a divisor ratio and the reset signal, and output divider number control signal.Type: ApplicationFiled: April 20, 2012Publication date: October 24, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Jen CHEN, Feng Wei KUO, Huan-Neng CHEN, Chewn-Pu JOU
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Patent number: 8547151Abstract: A die stack of an integrated circuit includes a plurality of dies. Each die in the die stack includes a phase lock loop (PLL). The PLLs in each of the dies share a loop filter and other corresponding circuits.Type: GrantFiled: February 28, 2012Date of Patent: October 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Wei Kuo, Shyh-An Chi, Huan-Neng Chen, Yen-Jen Chen, Chewn-Pu Jou
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Patent number: 8456207Abstract: A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. The second signal counting circuit is configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, and the second oscillating signal is generated in relation to the first oscillating signal. The comparator is configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value. The lock status unit is configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods.Type: GrantFiled: November 16, 2011Date of Patent: June 4, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Wei Kuo, Kyle Yen, Huan-Neng Chen, Yen-Jen Chen, Chewn-Pu Jou
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Publication number: 20130134553Abstract: Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise.Type: ApplicationFiled: January 30, 2012Publication date: May 30, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Feng Wei Kuo, Hui Yu Lee, Huan-Neng Chen, Yen-Jen Chen, Yu-Ling Lin, Chewn-Pu Jou
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Publication number: 20130135011Abstract: A phase frequency detector circuit includes an edge detector circuit, a plurality of phase frequency detector sub-circuits, and a decision circuit. The edge detector circuit is configured to receive a first input signal and a second input signal. The decision circuit is configured to detect whether a blind condition exits based on outputs of the edge detector circuit and outputs of the plurality of phase frequency detector sub-circuits. Responsive to a result of the decision circuit, a corresponding frequency detector sub-circuit of the plurality of phase frequency detector sub-circuit is configured to provide signals for use in determining a phase difference between the first input signal and the second input signal.Type: ApplicationFiled: November 30, 2011Publication date: May 30, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Jen CHEN, I-Ting LEE, Feng Wei KUO, Huan-Neng CHEN, Chewn-Pu JOU
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Publication number: 20130135018Abstract: A die stack of an integrated circuit includes a plurality of dies. Each die in the die stack includes a phase lock loop (PLL). The PLLs in each of the dies share a loop filter and other corresponding circuits.Type: ApplicationFiled: February 28, 2012Publication date: May 30, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng Wei KUO, Shyh-An CHI, Huan-Neng CHEN, Yen-Jen CHEN, Chewn-Pu JOU
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Publication number: 20130120035Abstract: A lock detector for a PLL circuit includes a first signal counting circuit, a second signal counting circuit, a comparator, and a lock status unit. The first signal counting circuit is configured to define a plurality of observation periods according to a first oscillating signal and a predetermined cycle value. The second signal counting circuit is configured to determine a maximum counter value according to a second oscillating signal within each of the observation periods, and the second oscillating signal is generated in relation to the first oscillating signal. The comparator is configured to determine, for each of the observation periods, whether the maximum counter value equals the predetermined cycle value. The lock status unit is configured to generate a lock signal based on the maximum counter value being equal to the predetermined cycle value for a predetermined number of consecutive ones of the observation periods.Type: ApplicationFiled: November 16, 2011Publication date: May 16, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng Wei KUO, Kyle YEN, Huan-Neng CHEN, Yen-Jen CHEN, Chewn-Pu JOU
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Patent number: 7554456Abstract: A radio frequency IC tag is provided which is excellent in weatherability, dustproofness, waterproofness, and static protection and capable of making a communication distance long even though each antenna section is made small in configuration. A first antenna equipped with an IC chip is formed on an upper surface of a first spacer. A second antenna is formed on a lower surface of a top cover. A second spacer is shaped in hollow form. The first spacer and the top cover are disposed on both sides of the second spacer with the first antenna and the second antenna being opposite to each other. Each of the first spacer, the second spacer and the top cover is formed of a synthetic resin. Thus, the IC chip and each antenna section are not exposed to the outside and hence weatherability is enhanced.Type: GrantFiled: March 8, 2006Date of Patent: June 30, 2009Assignee: MITAC Technology Corp.Inventor: Yen-Jen Chen