Patents by Inventor Yen-Ju Lu

Yen-Ju Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079787
    Abstract: An antenna structure includes a radiative antenna element disposed in a first conductive layer and a reference ground plane, disposed in a second conductive layer under the first conductive layer. The radiative antenna element is loaded with a plurality of slots and is electrically connected to the reference ground plane through a plurality of vias, and the vias are placed along a first line of the radiative antenna element and the slots are placed along a second line perpendicular to the first line.
    Type: Application
    Filed: August 14, 2023
    Publication date: March 7, 2024
    Applicant: MEDIATEK INC.
    Inventors: Debapratim Dhara, Shih-Chia Chiu, Yen-Ju Lu, Sheng-Mou Lin
  • Publication number: 20240038690
    Abstract: A semiconductor device includes an electronic device, a guard trace and a first trace. The guard trace is connecting to a ground layer through a first ground via. The first trace is disposed adjacent to the electronic device and the guard trace and includes a first segment. A phase or a direction of a first current signal conducted on the first trace is changed in the first segment. The electronic device and the first trace are disposed at different sides of the guard trace and the first ground via is beside the first segment.
    Type: Application
    Filed: June 19, 2023
    Publication date: February 1, 2024
    Applicant: MEDIATEK INC.
    Inventors: Po-Jui Li, Ruey-Bo Sun, Yen-Ju Lu, Chun-Yuan Yeh, Sheng-Mou Lin
  • Patent number: 11848481
    Abstract: A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, a molding compound disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the molding compound. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.
    Type: Grant
    Filed: April 4, 2022
    Date of Patent: December 19, 2023
    Assignee: MediaTek Inc.
    Inventors: Shih-Chia Chiu, Yen-Ju Lu, Wen-Chou Wu, Nan-Cheng Chen
  • Patent number: 11837552
    Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: December 5, 2023
    Assignee: MediaTek Inc.
    Inventors: Wen-Sung Hsu, Tao Cheng, Nan-Cheng Chen, Che-Ya Chou, Wen-Chou Wu, Yen-Ju Lu, Chih-Ming Hung, Wei-Hsiu Hsu
  • Patent number: 11821975
    Abstract: A radar module includes a printed circuit board (PCB) and a semiconductor package mounted on the PCB. The semiconductor package comprises an integrated circuit die and a substrate for electrically connecting the integrated circuit die to the PCB. The substrate comprises an antenna layer integrated into the semiconductor package and electrically connected to the integrated circuit die for at least one of transmitting and receiving radar signals. A discrete pattern-shaping device is mounted on the PCB and is configured to shape a radiation pattern of the radar signals.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: November 21, 2023
    Assignee: MediaTek Inc.
    Inventors: Yen-Ju Lu, Chih-Ming Hung, Wen-Chou Wu
  • Patent number: 11764475
    Abstract: An antenna structure includes a radiative antenna element disposed in a first conductive layer and a reference ground plane, disposed in a second conductive layer under the first conductive layer. The radiative antenna element is loaded with a plurality of slots and is electrically connected to the reference ground plane through a plurality of vias, and the vias are placed along a first line of the radiative antenna element and the slots are placed along a second line perpendicular to the first line.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: September 19, 2023
    Assignee: MEDIATEK INC.
    Inventors: Debapratim Dhara, Shih-Chia Chiu, Yen-Ju Lu, Sheng-Mou Lin
  • Patent number: 11720486
    Abstract: The present disclosure provides a memory data access apparatus and method thereof. The memory data access apparatus includes a cache memory and a processing unit. The processing unit is configured to: execute a memory read instruction, wherein the memory read instruction includes a memory address; determine that access of the memory address in the cache memory is missed; determine that the memory address is within a memory address range, wherein the memory address range corresponds to a data access amount; and read data blocks corresponding to the data access amount from the memory address of a memory.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: August 8, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yen-Ju Lu, Chao-Wei Huang
  • Patent number: 11624758
    Abstract: A test kit for testing a device under test (DUT) includes a socket structure for containing the DUT. The DUT includes an antenna and radiates a RF signal. The test kit further includes a reflector having a lower surface. The RF signal emitted from the antenna of the DUT is reflected by the reflector and a reflected RF signal is received by the antenna of the DUT.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: April 11, 2023
    Assignee: MEDIATEK INC.
    Inventors: Sheng-Wei Lei, Chang-Lin Wei, Ying-Chou Shih, Yeh-Chun Kao, Yen-Ju Lu, Po-Sen Tseng
  • Patent number: 11506710
    Abstract: A circuit system includes a first circuit, a second circuit, and a comparator. The second circuit and the first circuit have substantially identical structures. In a testing mode, the circuit system controls the first circuit and the second circuit to perform the same testing operation synchronously. During the process of the testing operation, the comparator keeps compares a first intermediate signal internally generated by the first circuit and a second intermediate signal corresponding to the first intermediate signal that is internally generated by the second circuit. When the first intermediate signal is different from the second intermediate signal, the circuit system controls the first circuit and the second circuit to stop the testing operation and controls the first circuit and the second circuit to perform a scan dump operation in order to record signals transmitting by the first circuit and signals transmitting by the second circuit.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: November 22, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Yen-Ju Lu
  • Patent number: 11500776
    Abstract: A data write system includes a processor circuit, a first memory, at least one register, and a second memory. The first memory is coupled to the processor circuit. The at least one register is configured to define at least one range. The second memory is coupled to the first memory. If a cache miss occurs and an access address of a reading command is in the at least one range in the second memory, a predetermined amount of data corresponding to the access address is written from the second memory into at least one first way of the first memory.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: November 15, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Yen-Ju Lu
  • Patent number: 11494305
    Abstract: A linked list searching method and device are configured to search a linked list by using a cache memory. The method includes the operations of: writing the linked list in a memory; writing the data of a first node in a first row of a tag memory of the cache memory, and writing an address of the first node in a first row of a data memory of the cache memory; writing the data of a second node in a second row of the tag memory, and writing the address of the second node in a second row of the data memory; and searching the data of the second node in the tag memory to directly retrieve the address of the second node when searching the address of the second node in the linked list according to the data of the second node.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: November 8, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Yen-Ju Lu
  • Publication number: 20220352084
    Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.
    Type: Application
    Filed: May 19, 2022
    Publication date: November 3, 2022
    Applicant: MediaTek Inc.
    Inventors: Wen-Sung Hsu, Tao Cheng, Nan-Cheng Chen, Che-Ya Chou, Wen-Chou Wu, Yen-Ju Lu, Chih-Ming Hung, Wei-Hsiu Hsu
  • Publication number: 20220349940
    Abstract: A circuit system includes a first circuit, a second circuit, and a comparator. The second circuit and the first circuit have substantially identical structures. In a testing mode, the circuit system controls the first circuit and the second circuit to perform the same testing operation synchronously. During the process of the testing operation, the comparator keeps compares a first intermediate signal internally generated by the first circuit and a second intermediate signal corresponding to the first intermediate signal that is internally generated by the second circuit. When the first intermediate signal is different from the second intermediate signal, the circuit system controls the first circuit and the second circuit to stop the testing operation and controls the first circuit and the second circuit to perform a scan dump operation in order to record signals transmitting by the first circuit and signals transmitting by the second circuit.
    Type: Application
    Filed: July 29, 2021
    Publication date: November 3, 2022
    Inventor: YEN-JU LU
  • Publication number: 20220302574
    Abstract: A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, a molding compound disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the molding compound. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.
    Type: Application
    Filed: April 4, 2022
    Publication date: September 22, 2022
    Applicant: MediaTek Inc.
    Inventors: Shih-Chia Chiu, Yen-Ju Lu, Wen-Chou Wu, Nan-Cheng Chen
  • Publication number: 20220269608
    Abstract: A linked list searching method and device are configured to search a linked list by using a cache memory. The method includes the operations of: writing the linked list in a memory; writing the data of a first node in a first row of a tag memory of the cache memory, and writing an address of the first node in a first row of a data memory of the cache memory; writing the data of a second node in a second row of the tag memory, and writing the address of the second node in a second row of the data memory; and searching the data of the second node in the tag memory to directly retrieve the address of the second node when searching the address of the second node in the linked list according to the data of the second node.
    Type: Application
    Filed: April 21, 2021
    Publication date: August 25, 2022
    Inventor: YEN-JU LU
  • Patent number: 11385894
    Abstract: A processor circuit is provided. The processor circuit includes an instruction decode unit, an instruction detector, an address generator and a data buffer. The instruction decode unit is configured to decode a load instruction to generate a decoding result. The instruction detector, coupled to the instruction decode unit, is configured to detect if the load instruction is in a load-use scenario. The address generator, coupled to the instruction decode unit, is configured to generate a first address requested by the load instruction according to the decoding result. The data buffer is coupled to the instruction detector and the address generator. When the instruction detector detects that the load instruction is in the load-use scenario, the data buffer is configured to store the first address generated from the address generator, and store data requested by the load instruction according to the first address.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: July 12, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yen-Ju Lu, Chao-Wei Huang
  • Patent number: 11373957
    Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: June 28, 2022
    Assignee: MediaTek Inc.
    Inventors: Wen-Sung Hsu, Tao Cheng, Nan-Cheng Chen, Che-Ya Chou, Wen-Chou Wu, Yen-Ju Lu, Chih-Ming Hung, Wei-Hsiu Hsu
  • Patent number: 11322823
    Abstract: A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, an encapsulation layer disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the encapsulation layer. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.
    Type: Grant
    Filed: September 3, 2018
    Date of Patent: May 3, 2022
    Assignee: MediaTek Inc.
    Inventors: Shih-Chia Chiu, Yen-Ju Lu, Wen-Chou Wu, Nan-Cheng Chen
  • Publication number: 20220102859
    Abstract: An antenna structure includes a radiative antenna element disposed in a first conductive layer and a reference ground plane, disposed in a second conductive layer under the first conductive layer. The radiative antenna element is loaded with a plurality of slots and is electrically connected to the reference ground plane through a plurality of vias, and the vias are placed along a first line of the radiative antenna element and the slots are placed along a second line perpendicular to the first line.
    Type: Application
    Filed: August 24, 2021
    Publication date: March 31, 2022
    Applicant: MEDIATEK INC.
    Inventors: Debapratim Dhara, Shih-Chia Chiu, Yen-Ju Lu, Sheng-Mou Lin
  • Patent number: 11244913
    Abstract: A semiconductor package includes a substrate, an electronic component, a dielectric layer a transmitting antenna, a receiving antenna and a FSS (Frequency selective surface) antenna. The electronic component is disposed on and electrically connected with the substrate. The dielectric layer has a dielectric upper surface. The transmitting antenna and the receiving antenna are formed adjacent to the substrate. The FSS antenna is formed adjacent to the dielectric upper surface of the dielectric layer. The FSS antenna is separated from the substrate by the dielectric layer in a wireless signal emitting direction.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: February 8, 2022
    Assignee: MEDIATEK INC.
    Inventors: Ying-Chih Chen, Yen-Ju Lu, Che-Ya Chou, Hsing-Chih Liu