Abstract: An Antenna-in-Package (AiP) includes an interface layer having at least an antenna layer and an insulating layer disposed under the antenna layer. The antenna layer includes a first antenna region and a second antenna region spaced apart from the first antenna region. An integrated circuit die is disposed on the interface layer. The integrated circuit die is interposed between the first antenna region and the second antenna region. The first antenna region includes a first antenna element, a second antenna element extending along a first direction, and a feeding network electrically connecting the first antenna element and the second antenna element to the integrated circuit die. The feeding network, the first antenna element, and the second antenna element are coplanar. A plurality of solder balls is disposed on a surface of the interface layer.

Abstract: The present invention provides a temporary memory processing method including: receiving a write command including a write data and a write address; determining whether a corresponding temporary address is in a missed state to generate a determined result; and determining whether to write the write data into a corresponding buffer address of a buffer memory according to the determined result.

Abstract: A cache and a method for managing a cache are provided. The cache includes a storage circuit, a buffer circuit and a control circuit. The buffer circuit stores data in a first-in first-out (FIFO) manner. The control circuit is coupled to the storage circuit and the buffer circuit and is configured to find a storage space in the storage circuit and write the data to the storage space.

Abstract: An Antenna-in-Package (AiP) includes an interface layer, an integrated circuit die disposed on the interface layer, a molding compound disposed on the interface layer and encapsulating the integrated circuit die, and a plurality of solder balls disposed on a bottom surface of the interface layer. The interface layer includes an antenna layer, and an insulating layer between the antenna layer and the ground reflector layer. The antenna layer includes a first antenna region and a second antenna region spaced apart from the first antenna region. The integrated circuit die is interposed between the first antenna region and the second antenna region. The first antenna region is disposed adjacent to a first edge of the integrated circuit die, and the second antenna region is disposed adjacent to a second edge of the integrated circuit die, which is opposite to the first edge.

Abstract: An over-the-air (OTA) wireless test system includes a container, a machine plate disposed on the container, a supporter disposed on the machine plate, a load board disposed on the supporter, a socket disposed on the load board, a device under test (DUT) installed in the socket, and a wave-guiding feature in the socket and the load board configured to pass and guide electromagnetic waves to and/or from an antenna structure of the DUT. The wave-guiding feature comprises a wave-guiding channel in the socket defined by a plurality of pogo pins surrounding the antenna structure of the DUT. The wave-guiding feature may further comprise a radiation passage in the load board defined by rows of via fence extending through an entire thickness of the load board.

Abstract: The present invention discloses a data access device and method applicable to a processor. An embodiment of the data access device comprises: an instruction cache memory; a data cache memory; a processor circuit configured to read specific data from the instruction cache memory for the Nth time and read the specific data from the data cache memory for the Mth time, in which both N and M are positive integers and M is greater than N; a duplication circuit configured to copy the specific data from the instruction cache memory to the data cache memory when the processor circuit reads the specific data for the Nth time; and a decision circuit configured to determine whether data requested by a read request from the processor circuit are stored in the data cache memory according to the read request.

Abstract: A Radio Frequency (RF) device may include a plurality of antennas and one or more conductive traces configured to trap a portion of energy transmitted from at least one of the plurality of antennas. The one or more conductive traces are sized and positioned such that undesired coupling between the plurality of antennas may be suppressed while maintaining performance parameters of at least one of the plurality of antennas. The plurality of antennas and the one or more conductive traces may be formed using a redistribution layer coupled to a chip embedded in a molding layer.

Abstract: A wireless test system includes a load board having an upper surface and a lower surface. The load board has a testing antenna disposed on the load board. A socket for receiving a device under test (DUT) having an antenna structure therein is disposed on the upper surface of the load board. The antenna structure is aligned with the testing antenna. The wireless test system further includes a handler for picking up and delivering the DUT to the socket. The handler has a clamp for holding and pressing the DUT. The clamp is grounded during testing and functions as a ground reflector that reflects and reverses radiation pattern of the DUT from an upward direction to a downward direction toward the testing antenna.

Abstract: An antenna structure includes a radiative antenna element disposed in a first conductive layer, a reflector ground plane disposed in a second conductive layer under the first conductive layer, a feeding network comprising a transmission line disposed in a third conductive layer under the second conductive layer, and at least one coupling element disposed in proximity to a feeding terminal that electrically couples one end of the transmission line to the radiative antenna element. The coupling element is capacitively coupled with the feeding terminal.

Abstract: Various examples pertaining to a sensor housing design for millimeter wave (mmWave) sensors are described. A sensor housing may include a radar sensor, a printed circuit board (PCB), a radome and a PCB holder. The radar sensor may be capable of emitting a radio wave. The PCB may have a first side and a second side opposite the first side with the radar sensor mounted on the first side thereof to form a PCB assembly (PCBA). The radome may include a cavity in which the PCBA is disposed. The PCB holder may be disposed along a circumference of an inner wall of the radome, and the PCB holder may be configured to hold the PCBA such that a distance between an inner surface of the radome and a side of the radar sensor facing the inner surface of the radome is proportional to half wavelength of the radio wave.

Abstract: The present invention provides a temporary memory processing method including: receiving a write command including a write data and a write address; determining whether a corresponding temporary address is in a missed state to generate a determined result; and determining whether to write the write data into a corresponding buffer address of a buffer memory according to the determined result.

Abstract: A radar module includes a printed circuit board (PCB) and a semiconductor package mounted on the PCB. The semiconductor package comprises an integrated circuit die and a substrate for electrically connecting the integrated circuit die to the PCB. The substrate comprises an antenna layer integrated into the semiconductor package and electrically connected to the integrated circuit die for at least one of transmitting and receiving radar signals. A discrete pattern-shaping device is mounted on the PCB and is configured to shape a radiation pattern of the radar signals.

Abstract: An Antenna-in-Package (AiP) includes an interface layer, an integrated circuit die disposed on the interface layer, a molding compound disposed on the interface layer and encapsulating the integrated circuit die, and a plurality of solder balls disposed on a bottom surface of the interface layer. The interface layer includes an antenna layer, and an insulating layer between the antenna layer and the ground reflector layer. The antenna layer includes a first antenna region and a second antenna region spaced apart from the first antenna region. The integrated circuit die is interposed between the first antenna region and the second antenna region. The first antenna region is disposed adjacent to a first edge of the integrated circuit die, and the second antenna region is disposed adjacent to a second edge of the integrated circuit die, which is opposite to the first edge.

Abstract: A semiconductor package includes a substrate having thereon at least an antenna layer and a ground reflector layer under the antenna layer, a radio frequency (RF) die disposed on or in the substrate, an encapsulation layer disposed on the antenna layer of the substrate, and a frequency-selective surface (FSS) structure disposed on the encapsulation layer. The FSS structure is a two-dimensional periodic array of metal patterns of same shape and size. The FSS structure has highly reflective characteristic.

Abstract: An over-the-air (OTA) wireless test system includes a container, a machine plate disposed on the container, a supporter disposed on the machine plate, a load board disposed on the supporter, a socket disposed on the load board, a device under test (DUT) installed in the socket, and a wave-guiding feature in the socket and the load board configured to pass and guide electromagnetic waves to and/or from an antenna structure of the DUT. The wave-guiding feature comprises a wave-guiding channel in the socket defined by a plurality of pogo pins surrounding the antenna structure of the DUT. The wave-guiding feature may further comprise a radiation passage in the load board defined by rows of via fence extending through an entire thickness of the load board.

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.

Abstract: The present invention discloses a data access device and method applicable to a processor. An embodiment of the data access device comprises: an instruction cache memory; a data cache memory; a processor circuit configured to read specific data from the instruction cache memory for the Nth time and read the specific data from the data cache memory for the Mth time, in which both N and M are positive integers and M is greater than N; a duplication circuit configured to copy the specific data from the instruction cache memory to the data cache memory when the processor circuit reads the specific data for the Nth time; and a decision circuit configured to determine whether data requested by a read request from the processor circuit are stored in the data cache memory according to the read request.

Abstract: A Radio Frequency (RF) device may include a plurality of antennas and one or more conductive traces configured to trap a portion of energy transmitted from at least one of the plurality of antennas. The one or more conductive traces are sized and positioned such that undesired coupling between the plurality of antennas may be suppressed while maintaining performance parameters of at least one of the plurality of antennas. The plurality of antennas and the one or more conductive traces may be formed using a redistribution layer coupled to a chip embedded in a molding layer.

Abstract: A Radio Frequency (RF) device may include a plurality of antennas and one or more conductive traces configured to trap a portion of energy transmitted from at least one of the plurality of antennas. The one or more conductive traces are sized and positioned such that undesired coupling between the plurality of antennas may be suppressed while maintaining performance parameters of at least one of the plurality of antennas. The plurality of antennas and the one or more conductive traces may be formed using a redistribution layer coupled to a chip embedded in a molding layer.

Abstract: A management method of a virtual-to-physical address translation system includes the following steps: providing a first storage space, wherein the first storage space includes a plurality of buffer entries; providing a second storage space, wherein the second storage space includes a plurality of translation entries, and the translation entries correspond to a plurality of translation indices; and when receiving a write instruction to write a first virtual-to-physical address translation into a specific buffer entry of the buffer entries, storing the first virtual-to-physical address translation in a write translation entry of the translation entries according to a first part of bits of a first virtual address corresponding to the first virtual-to-physical address translation, and storing the first virtual address and a write translation index corresponding to the write translation entry in the specific buffer entry.