Abstract: In some embodiments, the invention involves utilizing a tree merge sort in a platform to minimize cache reads/writes when sorting large amounts of data. An embodiment uses blocks of pre-sorted data residing in “leaf nodes” residing in memory storage. A pre-sorted block of data from each leaf node is read from memory and stored in faster cache memory. A tree merge sort is performed on the nodes that are cache resident until a block of data migrates to a root node. Sorted blocks reaching the root node are written to memory storage in an output list until all pre-sorted data blocks have been moved to cache and merged upward to the root. The completed output list in memory storage is a list of the fully sorted data. Other embodiments are described and claimed.

Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

Abstract: An interpolation unit, such as may be found in a texture unit or texture sampler, may be used utilized to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to an interpolation unit. The interpolation unit may use linear interpolators in order to perform the dot product calculations.

Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

Abstract: Embodiments of shared cache memories for multi-core processors are presented. In one embodiment, a cache memory comprises a group of sampling cache sets and a controller to determine a number of misses that occur in the group of sampling cache sets. The controller is operable to determine a victim cache line for a cache set based at least in part on the number of misses.

Abstract: Method, apparatus, and program means for performing a parallel table lookup using SIMD instructions. The method of one embodiment comprises loading a table having a set of L data elements. A determination of whether the table fits into a single register is made. A data lookup into the table is performed with a packed data shuffle operation if the determination indicates that the table does fit into a single register. The table is divided into a plurality of sections if the table does not fit into a single register. Each of the sections is sized to fit into a single register. A plurality of packed data shuffle operations are executed on the plurality of sections to look up data in the table.

Abstract: In one embodiment, the present invention includes a directory of a private cache hierarchy to maintain coherency between data stored in the cache hierarchy, where the directory is to enable concurrent cache-to-cache transfer of data to two private caches. Other embodiments are described and claimed.

Abstract: A method and apparatus for performing matrix transformations including multiply-add operations and byte shuffle operations on packed data in a processor. In one embodiment, two rows of content byte elements are shuffled to generate a first and second packed data respectively including elements of a first two columns and of a second two columns. A third packed data including sums of products is generated from the first packed data and elements from two rows of a matrix by a multiply-add instruction. A fourth packed data including sums of products is generated from the second packed data and elements from two more rows of the matrix by another multiply-add instruction. Corresponding sums of products of the third and fourth packed data are then summed to generate two rows of a product matrix. Elements of the product matrix may be generated in an order that further facilitates a second matrix multiplication.

Abstract: Activities may be delayed from being dispatched until another activity is ready to be dispatched. Dispatching more than activities increase overlapping in execution time of activities. By delaying the dispatch of the activities, power consumption and thermal dissipation on a multi-threading processor may be reduced.

Abstract: An apparatus to detect streaming data in memory is presented. In one embodiment the apparatus use reuse bits and S-bits status for cache lines wherein an S-bit status indicates the data in the cache line are potentially streaming data. To enhance the efficiency of a cache, different measures can be applied to make the streaming data become the next victim during a replacement.

Abstract: Method, apparatus, and program means for rearranging data between multiple registers. The method of one embodiment comprises shuffling first set of packed data from a first source based on a first set of masks to produce a first set of shuffled data. The first set of masks is to include a first plurality of control entries to set designated data element positions in the first set of shuffled data to zero. A second packed data from a second source is shuffled based on a second set of masks to produce a second set of shuffled data. The second set of masks includes a second plurality of control entries to set to zero data element positions in the second set of shuffled data opposite to said designated data element positions in the first set of shuffled data. The first set of shuffled data and said second set of shuffled data are merged together to form a packed data resultant.

Abstract: In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data from a second class to the first class based on the determination, and moving the data to a first portion of a shared cache associated with a first requester unit based on the re-classification. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.

Abstract: Embodiments of the invention relate to a method and system for caching data in a multiple-core system with shared cache. According to the embodiments, data used by the cores may be classified as being of one of predetermined types. The classification may enable efficiencies to be realized by performing different types of handling corresponding to different data types. For example, data classified as likely to be re-used may be stored in a shared cache, in a region of the shared cache that is closest to a core using the data. By storing the data this way, access time and energy consumption may be reduced if the data is subsequently retrieved for use by the core.

Abstract: In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data from a second class to the first class based on the determination, and moving the data to a first portion of a shared cache associated with a first requester unit based on the re-classification. Other embodiments are described and claimed.

Abstract: In an encoding process, video data are represented as a bitstream of a quantized base layer and at least two enhancement layers, with each picture in each layer identified by a start code. The base layer, plus a number of enhancement layers capable of being transmitted by the communication channel's bandwidth, are transmitted on the communication channel.

Abstract: A system and method for the design and operation of a cache system with differing cache location lengths in level one caches is disclosed. In one embodiment, each level one cache may include groups of cache locations of differing length, capable of holding portions of a level two cache line. A state tree may be created from data in a sharing vector. When a request arrives from a level one cache, the level two cache may examine the nodes of the state tree to determine whether the node of the state tree corresponding to the incoming request is already active. The results of this determination may be used to inhibit or permit the concurrent processing of the request.

Abstract: A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory has stored therein at least a first packed data. The processor performs operations on data elements in the first packed data to generate a plurality of data elements in a second packed data in response to receiving an instruction. At least two of the plurality of data elements in the second packed data store the results of an intra-add operation, at least one of these results coming from the operation on data elements of the first packed data. One embodiment of a software method utilizes horizontal intra-add instructions for performing butterfly computations as may be employed, for example, in Walsh-Hadamard transforms or in Fast-Fourier Transforms.

Abstract: A method and system of motion estimation for video data compression is disclosed. Individual frames of video data are divided into blocks of pixels. One frame is searched to find a block of pixels that matches intensity with the block of pixels from a second frame. In one embodiment, a motion estimator performs a rhombus shaped search of progressively smaller range for a matching block of pixels. In one embodiment, prediction motion vector is used to reduce the search efforts. In one embodiment, the actual shape of the rhombus can be adjusted to the type of motion expected.

Abstract: In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data from a second class to the first class based on the determination, and moving the data to a first portion of a shared cache associated with a first requester unit based on the re-classification. Other embodiments are described and claimed.