Abstract: Management of resources in a computer system can reduce energy consumption of the system. This can be accomplished by monitoring application states for the software applications and/or monitoring thread states in a multi-threading system, and then makes resource adjustments in the system. The application states monitoring may be performed by monitoring the data buffers set up for temporary data used by software applications. Depending on the buffer levels, resources may be increased or decreased. Adjustments of resources may come in the form of changing the voltage and frequency of the processors in the system, and other means. Decreasing the resources may help reduce energy consumption. Management of resources may also be performed by monitoring the threads associated with one or multiple software applications in the system and controlling the dispatch of threads. A ready thread may be delayed to increase the opportunity for concurrent running of multiple threads.

Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

Abstract: A cache management operation. In one embodiment, a first recall value for a first unit of data is generated, a second recall value for a second unit of data is generated, and the first and second recall values are compared. The unit of data having the higher recall value is stored in a first section of a storage device. The unit of data having the lower recall value is stored in a second section of a storage device. A greater amount of compression is performed on the unit of data having the lower recall value.

Abstract: A method and apparatus for storing image/video data in a memory device. The method includes receiving an image consisting of a plurality of pixels. In addition, the method includes generating addresses in the memory device for pixels from the image, wherein the memory addresses are generated within memory blocks consisting of multiple rows, wherein each row of the memory block is shorter in length than a full line of the memory device, wherein each memory block is aligned within a boundary of the memory device.

Abstract: A method and apparatus for variable length coding is described. A method comprises receiving a group of data having a group of set values, identifying a group of positions of the group of set values within the group of data without branching, for each of the group of positions, encoding a run of non-set values preceding each of the group of positions.

Abstract: A method for dequantizing quantized data is provided, where the quantized data includes multiple encoded versions of source data. An initial encoding of the source data is received, where the initial encoding includes a sequence of quantized symbols. At least one additional encoding of the source data is received, where the at least one additional encoding includes a sequence of quantized symbols. The initial encoding and the at least one additional encoding are independently encoded. The initial encoding and the at least one additional encoding are aligned. A quantization interval of a symbol in the initial encoding is determined. A quantization interval of a corresponding symbol in the at least one additional encoding is determined. An intersection of the quantization intervals of the symbol in the initial encoding and the corresponding symbol in at least one additional encoding is determined. Based on the intersection, a dequantized symbol is generated.

Abstract: An apparatus and method for extracting and loading data to/from a buffer are described. The method includes the selection of data from a data buffer in response to execution of a data access instruction. The data buffer includes a plurality of data storage devices, one or more of which initially contain the selected data. Accordingly, the plurality of data storage devices form a single address space that is addressable at a bit-level. When the selected data spans from a source data storage device to a next data storage device of the data buffer, a portion of the selected data from source data storage device is concatenated with a remaining portion of the selected data from the next data storage device to form the selected data as a contiguous unit. Finally, once the selected data is formed, the selected data is stored within a destination data storage device.

Abstract: A method and apparatus for performing bi-linear interpolation and motion compensation including multiply-add operations and byte shuffle operations on packed data in a processor. In one embodiment, two or more lines of 2n+1 content byte elements may be shuffled to generate a first and second packed data respectively including at least a first and a second 4n byte elements including 2n−1 duplicated elements. A third packed data including sums of products is generated from the first packed data and packed byte coefficients by a multiply-add instruction. A fourth packed data including sums of products is generated from the second packed data and elements and packed byte coefficients by another multiply-add instruction. Corresponding sums of products of the third and fourth packed data are then summed, and may be rounded and averaged.

Abstract: A method and apparatus for performing matrix transformations including multiply-add operations and byte shuffle operations on packed data in a processor. In one embodiment, two rows of content byte elements are shuffled to generate a first and second packed data respectively including elements of a first two columns and of a second two columns. A third packed data including sums of products is generated from the first packed data and elements from two rows of a matrix by a multiply-add instruction. A fourth packed data including sums of products is generated from the second packed data and elements from two more rows of the matrix by another multiply-add instruction. Corresponding sums of products of the third and fourth packed data are then summed to generate two rows of a product matrix. Elements of the product matrix may be generated in an order that further facilitates a second matrix multiplication.

Abstract: Activites may be delayed from being dispatched until anther activity is ready to be dispatched. Dispatching more than one activities increase overlapping in execution time of activities. By delaying the dispatch of the activities, power consumption and thermal dissipation on a multi-threading processor may be reduced.

Abstract: An apparatus and method for performing data access in accordance with memory access patterns are described. In one embodiment, the method includes the determination, in response to a memory access instruction, of a memory access pattern of data requested by the memory access instruction. Once the memory access pattern is determined, the data requested by the memory access instruction is accessed according to the determined memory access pattern. Finally, once the data is accessed, the data is processed according to the memory access instruction. Accordingly, in this embodiment of the present invention, data is accessed according to memory access patterns including zig-zag patterns scan, Zerotree scan, bit plane extraction, fine granularity scalability or the like.

Abstract: An apparatus and method facilitating memory data access with generic read/write patterns are described. In one embodiment, the method includes the detection, in response to a load instruction, of a cache hit/cache miss of data requested by the load instruction within a re-tiling (RT) cache. When a cache miss is detected, a block of data is loaded into the RT cache according to the load instruction. This block of data will contain the data requested by the load instruction. Once loaded, a non-horizontally sequential access of the data requested by the load instruction is performed from the RT cache. Finally, the data accessed from the RT cache may be stored into a destination data storage device according to the load instruction.

Abstract: A method and apparatus for including in a processor instructions for performing horizontal intra-add operations on packed data. One embodiment of the processor is coupled to a memory. The memory has stored therein at least a first packed data. The processor performs operations on data elements in the first packed data to generate a plurality of data elements in a second packed data in response to receiving an instruction. At least two of the plurality of data elements in the second packed data store the results of an intra-add operation, at least one of these results coming from the operation on data elements of the first packed data. One embodiment of a software method utilizes horizontal intra-add instructions for performing butterfly computations as may be employed, for example, in Walsh-Hadamard transforms or in Fast-Fourier Transforms.

Abstract: Method, apparatus, and program means for rearranging data between multiple registers. The method of one embodiment comprises shuffling first set of packed data from a first source based on a first set of masks to produce a first set of shuffled data. The first set of masks is to include a first plurality of control entries to set designated data element positions in the first set of shuffled data to zero. A second packed data from a second source is shuffled based on a second set of masks to produce a second set of shuffled data. The second set of masks includes a second plurality of control entries to set to zero data element positions in the second set of shuffled data opposite to said designated data element positions in the first set of shuffled data. The first set of shuffled data and said second set of shuffled data are merged together to form a packed data resultant.

Abstract: Method, apparatus, and program means for performing a parallel table lookup using SIMD instructions. The method of one embodiment comprises loading a table having a set of L data elements. A determination of whether the table fits into a single register is made. A data lookup into the table is performed with a packed data shuffle operation if the determination indicates that the table does fit into a single register. The table is divided into a plurality of sections if the table does not fit into a single register. Each of the sections is sized to fit into a single register. A plurality of packed data shuffle operations are executed on the plurality of sections to look up data in the table.

Abstract: A pixel padding procedure is disclosed. The padding procedure provides a method for filling pixels in a block in accordance with intensities of pixels in preceding and succeeding pixels of the same row or column. This padding procedure may include filling pixels with simultaneous logic operations; transposing blocks before and after horizontal padding; case detecting for simple or complex padding; simple pixel filling, where no pixels need to be averaged; and complex pixel filling, which contains pixels to be averaged. In one embodiment, this procedure may be performed in an MMX™ implementation for MPEG-4 repetitive padding.

Abstract: A novel storage format enabling a method for improved memory management of video images is described. The method includes receiving an image consisting of a plurality of color components. Once received, the plurality of color components is converted to a mixed format of planar format and packed format. The mixed packet format is implemented by storing one or more of the plurality of color components in a planar format and storing one or more of the plurality of color components in a packed format. A method for writing out video images is also described utilizing a write combining (WC) fame buffer. The decoding method motion compensates groups of macroblocks in order to eliminate partial writes from the WC frame buffer.

Abstract: A method and apparatus for variable length coding is described. A method comprises receiving a group of data having a group of set values, identifying a group of positions of the group of set values within the group of data without branching, for each of the group of positions, encoding a run of non-set values preceding each of the group of positions.

Abstract: In an encoding or decoding process for compressible data, non-raster ordered bitstreams of transform data are rearranged in memory so later data access is contiguous, efficiently allowing processing in a single cache line. In an encoder, rearrangement can utilize a buffer copy that enables address calculation to performed only once per block.

Abstract: A cache management operation. In one embodiment, a first recall value for a first unit of data is generated, a second recall value for a second unit of data is generated, and the first and second recall values are compared. The unit of data having the higher recall value is stored in a first section of a storage device. The unit of data having the lower recall value is stored in a second section of a storage device. A greater amount of compression is performed on the unit of data having the lower recall value.