Abstract: In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data from a second class to the first class based on the determination, and moving the data to a first portion of a shared cache associated with a first requester unit based on the re-classification. Other embodiments are described and claimed.

Abstract: A novel storage format enabling a method for improved memory management of video images is described. The method includes receiving an image consisting of a plurality of color components. Once received, the plurality of color components is converted to a mixed format of planar format and packed format. The mixed packet format is implemented by storing one or more of the plurality of color components in a planar format and storing one or more of the plurality of color components in a packed format. A method for writing out video images is also described utilizing a write combining (WC) fame buffer. The decoding method motion compensates groups of macroblocks in order to eliminate partial writes from the WC frame buffer.

Abstract: A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion.

Abstract: Fractional parts of quantized video coefficients are used as enhancement layers when encoding a video steam. This use of the fractional parts allows the reuse of decoding components.

Abstract: Embodiments of the invention relate to a method and system for caching data in a multiple-core system with shared cache. According to the embodiments, data used by the cores may be classified as being of one of predetermined types. The classification may enable efficiencies to be realized by performing different types of handling corresponding to different data types. For example, data classified as likely to be re-used may be stored in a shared cache, in a region of the shared cache that is closest to a core using the data. By storing the data this way, access time and energy consumption may be reduced if the data is subsequently retrieved for use by the core.

Abstract: Some embodiments of the invention provide devices, systems and methods of cache coherence. For example, an apparatus in accordance with an embodiment of the invention includes a memory to store a memory line; and a cache controller logic to assign a first cache coherence state to the memory line in relation to a first component, and to assign a second, different, cache coherence state to the memory line in relation to a second, different, component.

Abstract: In one embodiment, the present invention includes a method for performing a first level task of an application in a first processor of a system and dynamically allocating a second level task of the application to one of the first processor and a second processor based on architectural feedback information. In this manner, improved scheduling and application performance can be achieved by better utilizing system resources. Other embodiments are described and claimed.

Abstract: An efficient implementation of n-point discrete cosine transform, n-point inverse discrete cosine transform, shape adaptive discrete cosine transform and shape adaptive inverse discrete cosine transform algorithms for multimedia compression and decompression optimization. An n-point DCT function is represented by a first equation having an input matrix, an output matrix and a matrix of predetermined values. An n-point IDCT function is represented by a second equation having an input matrix, an output matrix and a matrix of predetermined values. The multiplication operations within the matrix of predetermined values are paired, thereby reducing processor instructions. SIMD operations, MMX operations, VLSI implementation, single processor implementation, and vector processing are used to perform the algorithms.

Abstract: A photo module includes a sensor unit for detecting and transforming a light beam into an image; a lens module includes a lens set for receiving and focusing the light beam; and a focus-adjusting module, coupled to the lens set, for controlling the lens set to move without rotation to adjust the relative distance between the lens set and the sensor unit, thereby forcing the lens module to focus the light beam on the sensor unit.

Abstract: A lens module includes a driving apparatus, a rotary device, and a lens assembly. The rotary device includes a contact portion having a continuous ramp and is rotated by the driving apparatus. The lens assembly includes a guide portion which contacts the contact portion and a lens moving along with the guide portion. A rotation of the rotary device is driven by the driving apparatus and a displacement of the lens assembly is promoted by the rotation of the rotary device via the guide portion so that focus is achieved.

Abstract: An image capture module includes a housing, a camera unit, and a shielding element. In this case, the housing has a first opening. The camera unit is accommodated in the housing and is adjacent to the first opening. The first opening exposes at lest one portion of the camera unit. The shielding element is disposed between the camera unit and the housing. The shielding element is disposed around the camera unit such that the shielding element and the camera unit cover the first opening.

Abstract: A camera module includes a housing, and the housing has an opening. The housing having a magnetic material or the magnetic component disposed in the housing can be used to absorb both the particles surrounding the camera module and the particles entering the housing through the opening.

Abstract: A camera module includes a lens, an actuator, a first magnetic device and a second magnetic device. The actuator is for applying a driving force to move the lens. The first magnetic device is disposed on the lens. The second magnetic device is for incorporating with the first magnetic device to generate a controlling force. The controlling force is reverse to the driving force in direction. When the actuator applies the driving force to move the lens, the controlling force provided by the second magnetic device serves as a controlling force for the lens moving.

Abstract: An apparatus and method for performing data access in accordance with memory access patterns are described. In one embodiment, the method includes the determination, in response to a memory access instruction, of a memory access pattern of data requested by the memory access instruction. Once the memory access pattern is determined, the data requested by the memory access instruction is accessed according to the determined memory access pattern. Finally, once the data is accessed, the data is processed according to the memory access instruction. Accordingly, in this embodiment of the present invention, data is accessed according to memory access patterns including zig-zag patterns scan, Zerotree scan, bit plane extraction, fine granularity scalability or the like.

Abstract: A method and an apparatus to improve processor utilization in data mining have been disclosed. In one embodiment, the method includes representing a transaction data set with a prefix tree, and allocating the prefix tree in a depth first search order in a memory of the computing system during data mining of the transaction data set. Other embodiments have been claimed and described.

Abstract: A system and method for the design and operation of a cache system with differing cache location lengths in level one caches is disclosed. In one embodiment, each level one cache may include groups of cache locations of differing length, capable of holding portions of a level two cache line. A state tree may be created from data in a sharing vector. When a request arrives from a level one cache, the level two cache may examine the nodes of the state tree to determine whether the node of the state tree corresponding to the incoming request is already active. The results of this determination may be used to inhibit or permit the concurrent processing of the request.

Abstract: A system and method for the design and operation of a distributed shared cache in a multi-core processor is disclosed. In one embodiment, the shared cache may be distributed among multiple cache molecules. Each of the cache molecules may be closest, in terms of access latency time, to one of the processor cores. In one embodiment, a cache line brought in from memory may initially be placed into a cache molecule that is not closest to a requesting processor core. When the requesting processor core makes repeated accesses to that cache line, it may be moved either between cache molecules or within a cache molecule. Due to the ability to move the cache lines within the cache, in various embodiments special search methods may be used to locate a particular cache line.

Abstract: In an encoding or decoding process for compressible data, non-raster ordered bitstreams of transform data are rearranged in memory so later data access is contiguous, efficiently allowing processing in a single cache line. In an encoder, rearrangement can utilize a buffer copy that enables address calculation to performed only once per block.

Abstract: A novel storage format enabling a method for improved memory management of video images is described. The method includes receiving an image consisting of a plurality of color components. Once received, the plurality of color components is converted to a mixed format of planar format and packed format. The mixed packet format is implemented by storing one or more of the plurality of color components in a planar format and storing one or more of the plurality of color components in a packed format. A method for writing out video images is also described utilizing a write combining (WC) fame buffer. The decoding method motion compensates groups of macroblocks in order to eliminate partial writes from the WC frame buffer.

Abstract: An apparatus and method facilitating memory data access with generic read/write patterns are described. In one embodiment, the method includes the detection, in response to a load instruction, of a cache hit/cache miss of data requested by the load instruction within a re-tiling (RT) cache. When a cache miss is detected, a block of data is loaded into the RT cache according to the load instruction. This block of data will contain the data requested by the load instruction. Once loaded, a non-horizontally sequential access of the data requested by the load instruction is performed from the RT cache. Finally, the data accessed from the RT cache may be stored into a destination data storage device according to the load instruction.