Patents by Inventor Yen Lee

Yen Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145381
    Abstract: In some embodiments, the present disclosure relates an integrated chip including a substrate. A conductive interconnect feature is arranged over the substrate. The conductive interconnect feature has a base feature portion with a base feature width and an upper feature portion with an upper feature width. The upper feature width is narrower than the base feature width such that the conductive interconnect feature has tapered outer feature sidewalls. An interconnect via is arranged over the conductive interconnect feature. The interconnect via has a base via portion with a base via width and an upper via portion with an upper via width. The upper via width is wider than the base via width such that the interconnect via has tapered outer via sidewalls.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Inventors: Shin-Yi Yang, Hsin-Yen Huang, Ming-Han Lee, Shau-Lin Shue, Yu-Chen Chan, Meng-Pei Lu
  • Publication number: 20240139301
    Abstract: The disclosure provides a method of active immunotherapy for a cancer patient, comprising administering vaccines against Globo series antigens (i.e., Globo H, SSEA-3 and SSEA-4). Specifically, the method comprises administering Globo H-CRM197 (OBI-833/821) in patients with cancer. The disclosure also provides a method of selecting a cancer patient who is suitable as treatment candidate for immunotherapy. Exemplary immune response can be characterized by reduction of the severity of disease, including but not limited to, prevention of disease, delay in onset of disease, decreased severity of symptoms, decreased morbidity and delayed mortality.
    Type: Application
    Filed: November 19, 2021
    Publication date: May 2, 2024
    Inventors: Ming-Tain LAI, Cheng-Der Tony YU, I-Ju CHEN, Wei-Han LEE, Chueh-Hao YANG, Chun-Yen TSAO, Chang-Lin HSIEH, Chien-Chih OU, Chen-En TSAI
  • Publication number: 20240133536
    Abstract: A feature inspection lighting system includes an outer cover having a mounting structure at a first end thereof and defining an outer periphery at a second end thereof. The cover includes an inner surface between the first end and the second end. The inner surface has raised surfaces defined thereon. A plurality of light sources is coupled to the raised surfaces of the inner surface of the cover, and cables to provide electrical power to the light sources is routed between the raised surfaces of the outer cover. The outer periphery of the cover may have a cutout defined therein through which all or part of an object to be inspected can pass.
    Type: Application
    Filed: October 23, 2022
    Publication date: April 25, 2024
    Inventors: Boyun Wang, Roman Balak, Paul Lee Briel, Yen-Chia Chu
  • Publication number: 20240136221
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Shao-Kuan Lee, Hai-Ching Chen, Hsin-Yen Huang, Shau-Lin Shue, Cheng-Chin Lee
  • Patent number: 11967582
    Abstract: A multi-chip device includes a first material within a substrate. The first material has a first coefficient of thermal expansion different than a second coefficient of thermal expansion of the substrate. A first chip overlies a first portion of the first material and a first portion of the substrate. A second chip overlies a second portion of the first material and a second portion of the substrate. The first material is between the first portion of the substrate and the second portion of the substrate.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chin-Hua Wang, Po-Chen Lai, Shu-Shen Yeh, Tsung-Yen Lee, Po-Yao Lin, Shin-Puu Jeng
  • Publication number: 20240126002
    Abstract: A backlight module includes a light source, a first prism sheet disposed on the light source, and a light type adjustment sheet disposed on a side of the first prism sheet away from the light source and including a base and multiple light type adjustment structures. The multiple light type adjustment structures are disposed on the first surface of the base. Each light type adjustment structure has a first structure surface and a second structure surface connected to each other. The first structure surface of each light type adjustment structure and the first surface of the base form a first base angle therebetween, and the second structure surface of each light type adjustment structure and the first surface of the base form a second base angle therebetween. The angle of the first base angle is different from the angle of the second base angle.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 18, 2024
    Applicant: Coretronic Corporation
    Inventors: Chih-Jen Tsang, Chung-Wei Huang, Shih-Yen Cheng, Jung-Wei Chang, Han-Yuan Liu, Chun-Wei Lee
  • Publication number: 20240130043
    Abstract: An electronic device is disclosed. The electronic device includes a system board and a first set of electronic devices disposed over the system board. Each of the first set of electronic devices comprises a processing unit and a carrier carrying the processing unit. The electronic device also includes a first interconnection structure electrically connected with the processing unit through the carrier and configured to receive a first power from a first power supply unit and to transmit the first power to the processing unit.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Yen TING, Pao-Nan LEE, Hung-Chun KUO, Jung Jui KANG, Chang Chi LEE
  • Patent number: 11962581
    Abstract: A vehicle control method applied to a smart car key includes receiving a connection request sent by a mobile terminal, establishing a communication connection with the mobile terminal in response to the connection request, receiving identity information and authorization request information sent by the mobile terminal, determining whether the identity information is correct, and in response that the identity information is correct, sending pairing information to the mobile terminal in response to the authorization request information and sending the identity information to a vehicle to be controlled. The mobile terminal controls the vehicle through the pairing information and the identity information to perform at least one operation.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 16, 2024
    Assignees: FUDING PRECISION COMPONENTS (SHENZHEN) CO., LTD., FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventor: Chia-Yen Lee
  • Patent number: 11955441
    Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • Patent number: 11954279
    Abstract: A solid-state switch for an external system includes a cover member, a first solid-state transducer, a second transducer, a microcontroller, a user feedback device, and a switching circuit. The first transducer is mechanically coupled to the cover member and configured to generate first signals in response to a perturbation at the cover member. The second transducer is configured to generate second signals in response to the perturbation. The microcontroller is configured to obtain first data from the first signals, second data from the second signals, and determine user inputs in accordance with at least the first data, the second data, and an operational state of the solid-state switch. The user feedback device is configured to provide feedback to a user of the switch in accordance with a switching behavior of the switching circuit.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: April 9, 2024
    Assignee: UltraSense Systems, Inc.
    Inventors: Andrew Jonathan Wright, Hao-Yen Tang, Chien-Te Lee, Mo Maghsoudnia
  • Patent number: 11944412
    Abstract: A blood pressure detection device manufactured by a semiconductor process includes a substrate, a microelectromechanical element, a gas-pressure-sensing element, a driving-chip element, an encapsulation layer and a valve layer. The substrate includes inlet apertures. The microelectromechanical element and the gas-pressure-sensing element are stacked and integrally formed on the substrate. The encapsulation layer is encapsulated and positioned on the substrate. A flowing-channel space is formed above the microelectromechanical element and the gas-pressure-sensing element. The encapsulation layer includes an outlet aperture in communication with an airbag. The driving-chip element controls the microelectromechanical element, the gas-pressure-sensing element and valve units to transport gas.
    Type: Grant
    Filed: June 2, 2021
    Date of Patent: April 2, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Ying-Lun Chang, Ching-Sung Lin, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee, Chun-Yi Kuo, Tsung-I Lin
  • Patent number: 11946569
    Abstract: An actuating and sensing module is disclosed and includes a bottom plate, a gas pressure sensor, a thin gas transportation device and a cover plate. The bottom plate includes a pressure relief orifice, a discharging orifice and a communication orifice. The gas pressure sensor is disposed on the bottom plate and seals the communication orifice. The thin gas transportation device is disposed on the bottom plate and seals the pressure relief orifice and the discharging orifice. The cover plate is disposed on the bottom plate and covers the gas pressure sensor and the thin gas-transportation device. The cover plate includes an intake orifice. The thin gas transportation device is driven to inhale gas through the intake orifice, the gas is then discharged through the discharging orifice by the thin gas transportation device, and a pressure change of the gas is sensed by the gas pressure sensor.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: April 2, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Shih-Chang Chen, Jia-Yu Liao, Hung-Hsin Liao, Chung-Wei Kao, Chi-Feng Huang, Yung-Lung Han, Chang-Yen Tsai, Wei-Ming Lee
  • Patent number: 11945971
    Abstract: Provided is a graphene-based coating suspension comprising multiple graphene sheets, thin film coating of an anti-corrosive pigment or sacrificial metal deposited on graphene sheets, and a binder resin dissolved or dispersed in a liquid medium, wherein the multiple graphene sheets contain single-layer or few-layer graphene sheets selected from a pristine graphene material having essentially zero % of non-carbon elements, or a non-pristine graphene material having 0.001% to 47% by weight of non-carbon elements wherein the non-pristine graphene is selected from graphene oxide, reduced graphene oxide, graphene fluoride, graphene chloride, graphene bromide, graphene iodide, hydrogenated graphene, nitrogenated graphene, doped graphene, chemically functionalized graphene, or a combination thereof. The invention also provides a process for producing this coating suspension. Also provided is an object or structure coated at least in part with such a coating.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: April 2, 2024
    Assignee: Global Graphene Group, Inc.
    Inventors: Fan-Chun Meng, Yi-jun Lin, Shaio-yen Lee, Wen Y. Chiu, Aruna Zhamu, Bor Z. Jang
  • Patent number: 11944935
    Abstract: A gas detection purification device is disclosed and includes a main body, a purification unit, a gas guider, a gas detection module and a controlling-driving module. The main body includes an inlet, an outlet, an external socket and a gas-flow channel disposed between the inlet and the outlet. The purification unit is disposed in the gas-flow channel for filtering gas introduced through the gas-flow channel. The gas guider is disposed in the gas channel and located at a side of the purification unit. The gas is inhaled through the inlet, flows through the purification unit and is discharged out through the outlet. The gas detection module is plugged into or detached from the external socket. The controlling driving module is disposed within the main body and electrically connected to the gas guider to control the operation of the gas guider in an enabled state and a disabled state.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: April 2, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Yung-Lung Han, Chi-Feng Huang, Chang-Yen Tsai, Wei-Ming Lee, Tsung-I Lin
  • Patent number: 11937903
    Abstract: A blood pressure device includes a first blood pressure measuring device, a second blood pressure measuring device, and a controller. The first blood pressure measuring device is to be worn on a first position of a wrist so as to obtain a first blood pressure information of the first position. The second blood pressure measuring device is to be worn on a second position of the wrist so as to obtain a second blood pressure information of the second position. The controller is electrically coupled to the first blood pressure measuring device and the second blood pressure measuring device so as to adjust tightness between the expanders and the user's skin, respectively. The controller receives, processes, and calculates a pulse transit time between the first blood pressure information and the second blood pressure information, and the controller obtains at least one blood pressure value based on the pulse transit time.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: March 26, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Yung-Lung Han, Chi-Feng Huang, Chang-Yen Tsai, Wei-Ming Lee, Chun-Yi Kuo, Chin-Wen Hsieh
  • Publication number: 20240093927
    Abstract: Disclosed herein are systems and methods for a method for controlling the temperature of a surface. In some embodiments, the method includes applying a variable input to a heat pump (e.g., a Peltier) in thermal communication with the surface. The variable input may vary about a voltage and may include a powered period and an unpowered period. In some embodiments, the method includes measuring a temperature of an element in thermal communication with the surface, determining, based on the temperature of the element, whether a temperature of the surface is within a safe temperature range for a user in thermal communication with the surface, in response to determining the surface is not within the safe temperature range, adjusting the voltage of the variable input to the heat pump, and in response to determining the surface is within the safe temperature range, continuing operation of the variable input at the voltage.
    Type: Application
    Filed: September 29, 2022
    Publication date: March 21, 2024
    Inventors: Tylan A. TSCHOPP, Lauren Lynch CLAYTON, Ashok Samuel BASKAR, Christopher Lee GARBUTT, Zara Elizabeth JONES, Yen Lim Lee, Jianquan Li, Liangxiong Huang, Yunfei Zhong, Yamin Jiang
  • Publication number: 20240094834
    Abstract: An active stylus having physical writing function includes a tip shell including a first opening and a second opening, a first electrode including a first end protruded through the first opening of the tip shell and including a second end protruded through the second opening of the tip shell and entered a main body housing of the active stylus, wherein the first electrode includes conductive material. The tip shell includes non-conductive material. The first end of the first electrode is configured to leave colored traces on an object by physical friction caused between the first end of the first electrode and the object.
    Type: Application
    Filed: July 27, 2023
    Publication date: March 21, 2024
    Inventors: Shih-Yen LEE, Tzu-Yu TING, Yeh Sen-Fan CHUEH, Min-Hung LIN, Shih-Hsiung HSIAO
  • Patent number: 11935957
    Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chiang Wu, Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai, Cheng-Lung Hung, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 11935890
    Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi Peng, Chun-Chieh Lu, Meng-Hsuan Hsiao, Ling-Yen Yeh, Carlos H. Diaz, Tung-Ying Lee
  • Patent number: 11935783
    Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yen Huang, Shao-Kuan Lee, Cheng-Chin Lee, Hai-Ching Chen, Shau-Lin Shue