Abstract: An active stylus having physical writing function includes a tip shell including a first opening and a second opening, a first electrode including a first end protruded through the first opening of the tip shell and including a second end protruded through the second opening of the tip shell and entered a main body housing of the active stylus, wherein the first electrode includes conductive material. The tip shell includes non-conductive material. The first end of the first electrode is configured to leave colored traces on an object by physical friction caused between the first end of the first electrode and the object.

Abstract: Semiconductor device structures having gate structures with tunable threshold voltages are provided. Various geometries of device structure can be varied to tune the threshold voltages. In some examples, distances from tops of fins to tops of gate structures can be varied to tune threshold voltages. In some examples, distances from outermost sidewalls of gate structures to respective nearest sidewalls of nearest fins to the respective outermost sidewalls (which respective gate structure overlies the nearest fin) can be varied to tune threshold voltages.

Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.

Abstract: Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

Abstract: Dynamic tuning method for a specific absorption rate (SAR) is provided. The dynamic tuning method is applied to user equipment (UE). The dynamic tuning method may include the following steps: the UE may determine the back-off value corresponding to the current antenna state; and the UE may tune the conducted power of the radio frequency (RF) circuit of the UE based on the back-off value.

Abstract: An interconnect structure includes a dielectric layer, a first conductive feature, a hard mask layer, a conductive layer, and a capping layer. The first conductive feature is disposed in the dielectric layer. The hard mask layer is disposed on the first conductive feature. The conductive layer includes a first portion and a second portion, the first portion of the conductive layer is disposed over at least a first portion of the hard mask layer, and the second portion of the conductive layer is disposed over the dielectric layer. The hard mask layer and the conductive layer are formed by different materials. The capping layer is disposed on the dielectric layer and the conductive layer.

Abstract: Embodiments are disclosed for submersion detection and underwater depth and low-latency temperature estimation. In an embodiment, a method comprises: determining a first set of vertical accelerations obtained from an inertial sensor of a wearable device; determining a second set of vertical accelerations obtained from pressure data; determining a first feature associated with a correlation between the first and second sets of vertical accelerations; and determining that the wearable device is submerged or not submerged in water based on a machine learning model applied to the first feature. In another embodiment, a method comprises: determining a submersion state of a wearable device; and responsive to the submersion state being submerged, computing a forward estimate of water temperature based on measured ambient water temperature at the water surface, a temperature error lookup table, and a rate of change of the ambient water temperature.

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The diode may be coupled to drive transistor circuitry, a data loading transistor, and emission transistors. The drive transistor circuitry may include at least two transistor portions connected in series. The data loading transistor has a drain region connected to a data line and a source region connected directly to the drive transistor circuitry. The data line may be connected to and overlap the drain region of the data loading transistor. The data line and the source region of the data loading transistor are non-overlapping to reduce row-to-row crosstalk.

Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.

Abstract: An appressed antenna includes an antenna housing and a metal shell. The antenna housing comprising a housing and a planar antenna, where the planar antenna is bent with one part folded onto the inner surface of the housing and other part pressed onto the outer surface of the housing. The antenna housing is sleeve fitted to the metal shell with a gap between for the planar antenna to radiate. In this all-metal environment, the position of the antenna is close to the gap opening will increase radiation efficiency. By having at least a branch at the tail end of the appressed antenna, the appressed antenna can have a good return loss and antenna gain.

Abstract: A method includes forming a first redistribution structure over a carrier, where forming the first redistribution structure includes forming a plurality of first organic polymer layers over the carrier, and forming a plurality of first conductive lines in the plurality of first organic polymer layers, attaching a first package structure to the first redistribution structure, the first package structure including a first semiconductor die, a molding material that surrounds an entirety of a perimeter of the first semiconductor die, and a second redistribution structure on bottom surfaces of the first semiconductor die and the molding material, dispensing a first underfill into a first gap between the plurality of first conductive lines and the first package structure, bonding a substrate to the first redistribution structure using first conductive connectors, and dispensing a second underfill into a second gap between the substrate and the first redistribution structure.

Abstract: Integrated circuit (IC) devices include a metal-insulator-metal (MIM) capacitor having a top electrode plate, a bottom electrode plate, and a plurality of intermediate electrode plates between the top electrode plate and the bottom electrode plate. A plurality of dielectric layers may separate each of the electrode plates of the MIM capacitor from adjacent plates of the MIM capacitor. Each of the intermediate electrode plates may have a thickness that is greater than a thickness of the top electrode plate and the bottom electrode plate. By providing multiple intermediate electrode plates between the top and bottom electrode plates of the MIM capacitor, and allocating the greatest plate thicknesses to the intermediate plates, the capacitance density may be increased in a given area of the IC device, which may provide increased performance for the IC device.

Abstract: A method for detecting failure of vehicle is provided. The method obtains noise data of the vehicle from microphone units. The microphone units are arranged on different positions of the vehicle. The method detects sets of coordinate data of noise sound sources which is determined according to the noise data. The sets of coordinate data of the noise sound sources are relative sets of coordinate data. The method detects a noise type of each noise sound source according to the noise data. The method matches the sets of coordinate data and a modeled image of the vehicle, to determine an absolute coordinate data of each noise sound source in the vehicle. The method determines failure parts of the vehicle according to the noise type of each noise sound source and the absolute coordinate data. A related electronic device and a related non-transitory storage medium are provided.

Abstract: Disclosed are power machines and systems configured to provide autonomous or augmented control of the machines in a localized positioning environment in which GPS navigation is not available. Also disclosed are methods of providing augmented control of a power machine in such an environment.

Abstract: Integrated circuit (IC) devices include a metal-insulator-metal (MIM) capacitor having a top electrode plate, a bottom electrode plate, and a plurality of intermediate electrode plates between the top electrode plate and the bottom electrode plate. A plurality of dielectric layers may separate each of the electrode plates of the MIM capacitor from adjacent plates of the MIM capacitor. Each of the intermediate electrode plates may have a thickness that is greater than a thickness of the top electrode plate and the bottom electrode plate. By providing multiple intermediate electrode plates between the top and bottom electrode plates of the MIM capacitor, and allocating the greatest plate thicknesses to the intermediate plates, the capacitance density may be increased in a given area of the IC device, which may provide increased performance for the IC device.

Abstract: A multi-die package includes a plurality of non-active dies among the IC dies included in the multi-die package. The non-active dies may be included to reduce the amount of encapsulant material and/or an underfill material that is used in the multi-die package, which reduces the amount of CTE mismatch in the multi-die package. Moreover, a plurality of non-active dies may be positioned in an adjacent manner between two or more active IC dies. The use of a plurality of non-active dies in a particular area of the multi-die package increases the quantity of gaps in the multi-die package. The increased quantity of gaps in the multi-die package provides an increased amount of area in the multi-die package for stress and strain absorption, and enables more even distribution of stresses and strains in the multi-die package.

Abstract: In one aspect, the disclosed technology relates to nanopore sequencing with a polynucleotide comprising a plurality of nucleotides, wherein each nucleotide comprises a linker construct between two positions of the nucleotide, wherein the linker construct optionally comprises a reporter moiety corresponding to the identity of the nucleotide, and wherein the linker construct is a part of the cleavable cyclic loop nucleotide comprising a cleavable site. In some embodiments, the nucleotides further comprise arresting constructs for slowing or halting the polynucleotide translocation through a nanopore.

Abstract: A semiconductor package structure includes a substrate, a die and a conductive structure. The die is disposed on or within the substrate. The die has a first surface facing away from the substrate and includes a sensing region and a pad at the first surface of the die. The first surface of the die has a first edge and a second edge opposite to the first edge. The sensing region is disposed adjacent to the first edge. The pad is disposed away from the first edge. The conductive structure electrically connects the pad and the substrate. The sensing region has a first end distal to the first edge of the first surface of the die. A distance from the first end of the sensing region to a center of the pad is equal to or greater than a distance from the first end of the sensing region to the first edge of the first surface of the die.

Abstract: A casing structure includes a plurality of first position-limiting rod elements, a main casing element, a cover element and a first shielding element. The main casing element has an accommodating space. The cover element is detachably connected to the main casing element. The first shielding element is detachably connected to the main casing element or the cover element. When the casing structure is in a storage state, the first position-limiting rod elements are located in the accommodating space. Therefore, the casing structure provided by the present invention can improve convenience during transportation.

Abstract: A package structure is provided. The package structure includes a semiconductor die bonding on a first surface of a redistribution structure through first bonding elements, and a wall structure bonding on the first surface of the redistribution structure through second bonding elements. The wall structure includes a plurality of partitions laterally arranged in a discontinuous ring, and the semiconductor die is located within the discontinuous ring.