Abstract: The present invention discloses an electronic ballast with dimming control from power line sensing for a fluorescent lamp, comprising: a control voltage generator, used to generate a control voltage according to a switching count of a power line; an oscillator, used to generate an oscillating signal, wherein the oscillating signal is of a fixed frequency and has a rising voltage portion and a falling voltage portion; and a comparator, used to generate a high side gating signal according to voltage comparison of the oscillating signal and the control voltage.

Abstract: A gas-discharge lamp controller utilizing a novel preheating phase control mechanism, having: a supply voltage tracking reference voltages generator, biased between a supply voltage and a reference ground, for generating a first reference voltage which is proportional to the supply voltage; and a control unit, for generating a high threshold signal according to the first reference voltage and a saw-tooth signal, the peak value of the saw-tooth signal being proportional to the supply voltage, wherein the control unit has a preheating phase, the high threshold signal is coupled with the first reference voltage during the preheating phase, and the time duration of the preheating phase is set by a predetermined number of periods of the saw-tooth signal.

Abstract: This invention discloses a monolithic inductor including a body made by compressing a magnetic powder, a coil positioned in the body, and a permanent magnet positioned in the body and in a magnetic circuit formed by applying current to the coil. The monolithic inductor of this invention includes the magnetic body containing the permanent magnet and the coil. The permanent magnet in the magnetic circuit (path of magnetic flux lines) formed by applying current to the coil generates a reverse-bias magnetic field, thereby increasing the operating range of the magnetic body, the saturation current of the magnetic body, and the rated current of the inductor.

Abstract: The present invention discloses a single chip ballast controller, capable of providing brightness levels overview and brightness setting of a fluorescent lamp during power-on period, having: a switching detection circuit, used to generate a set signal, which changes from an inactive state to an active state when a supply voltage falls below a threshold voltage; a time-varying reference voltage generator, used to generate a time-varying reference voltage varying between a first level and a second level during a power-on period, wherein the time-varying reference voltage can be fixed at a level by the active state of the set signal during the power-on period; and a gating signal generator, used to generate a high side driving signal and a low side driving signal according to an error voltage between the time-varying reference voltage and a current sensing voltage.

Abstract: The present invention discloses an electronic ballast with dimming control from power line sensing for a fluorescent lamp, comprising: a line switching sensing circuit, used to generate a switching sensing signal by performing a voltage comparison operation on a DC voltage; an oscillating signal gating unit, used to gate an oscillating signal with a pulse signal to generate a gated oscillating signal, wherein the pulse width of the pulse signal is generated according to the switching sensing signal; and a non-overlapping driver, used to generate a high side driving signal and a low side driving signal according to the gated oscillating signal.

Abstract: The present invention discloses an electronic ballast with dimming control from power line sensing for a fluorescent lamp, comprising: a line switching sensing circuit, used to generate a switching sensing signal by performing a voltage comparison operation on a DC voltage, and generate a reset signal according to the off time of the power line; a control voltage generator, used to generate a control voltage according to the count of said switching sensing signal; a voltage controlled oscillator, used to generate an oscillating signal according to the control voltage; and a non-overlapping driver, used to generate a high side driving signal and a low side driving signal according to the oscillating signal.

Abstract: The present invention discloses an electronic ballast with dimming control from power line sensing for a fluorescent lamp, comprising: a line switching sensing circuit, used to generate a switching sensing signal by performing a voltage comparison operation on a DC voltage, and generate a reset signal according to the off time of the power line; a dimming voltage generator, used to generate a dimming voltage according to a count of the switching sensing signal; and a phase-controlled non-overlapping driver, used to generate a high side driving signal and a low side driving signal for delivering a lamp current according to the dimming voltage, wherein the dimming voltage is used to generate a phase, and the phase is used to generate the lamp current.

Abstract: The present invention relates a single chip ballast controller for step-dimming of a fluorescent lamp, comprising: a counting circuit, used to generate a switching count by counting the instances where the supply voltage falls below a threshold voltage; a reference voltage generator, used to generate a reference voltage proportional to the switching count; and a gating signal generator, used to generate a high side driving signal and a low side driving signal according to an error voltage between the reference voltage and a current sensing voltage to regulate the current sensing voltage at the reference voltage, wherein the current sensing voltage is proportional to a lamp current flowing through the fluorescent lamp.

Abstract: The present invention discloses an electronic ballast with dimming control from power line sensing for a fluorescent lamp, comprising: a control voltage generator, used to generate a control voltage according to a switching count of a power line; an oscillator, used to generate an oscillating signal, wherein the oscillating signal is of a fixed frequency and has a rising voltage portion and a falling voltage portion; and a comparator, used to generate a high side gating signal according to voltage comparison of the oscillating signal and the control voltage.

Abstract: This patent discloses a differential type level shifter, comprising: a differential pair of transistors, having a pair of gate terminals, a pair of drain terminals and a common source terminal, with the pair of gate terminals coupled to a first clock signal and a second clock signal; a current source, coupled between the common source terminal and a reference ground, used to provide a bias current; and a pair of loading resistors, having a common end and a pair of output ends, with the common end coupled to a power line, the pair of output ends coupled to the pair of drain terminals; wherein the pair of drain terminals are used to generate a set signal and a reset signal in response to the first clock signal and the second clock signal.

Abstract: A strained channel transistor is provided. The strained channel transistor comprises a substrate formed of a first material. A source region comprised of a second material is formed in a first recess in the substrate, and a drain region comprised of the second material is formed in a second recess in the substrate. A strained channel region formed of the first material is intermediate the source and drain region. A gate stack formed over the channel region includes a gate electrode overlying a gate dielectric. A gate spacer formed along a sidewall of the gate electrode overlies a portion of at least one of said source region and said drain region. A cap layer may be formed over the second material, and the source and drain regions may be silicided.

Abstract: The present invention discloses an electronic ballast with dimming control from power line sensing for a fluorescent lamp, comprising: a line switching sensing circuit, used to generate a switching sensing signal by performing a voltage comparison operation on a DC voltage, and generate a reset signal according to the off time of the power line; a control voltage generator, used to generate a control voltage according to the count of said switching sensing signal; a voltage controlled oscillator, used to generate an oscillating signal according to the control voltage; and a non-overlapping driver, used to generate a high side driving signal and a low side driving signal according to the oscillating signal.

Abstract: The present invention discloses an electronic ballast with dimming control from power line sensing for a fluorescent lamp, comprising: a line switching sensing circuit, used to generate a switching sensing signal by performing a voltage comparison operation on a DC voltage; an oscillating signal gating unit, used to gate an oscillating signal with a pulse signal to generate a gated oscillating signal, wherein the pulse width of the pulse signal is generated according to the switching sensing signal; and a non-overlapping driver, used to generate a high side driving signal and a low side driving signal according to the gated oscillating signal.

Abstract: The present invention discloses an electronic ballast with dimming control from power line sensing for a fluorescent lamp, comprising: a line switching sensing circuit, used to generate a switching sensing signal by performing a voltage comparison operation on a DC voltage, and generate a reset signal according to the off time of the power line; a dimming voltage generator, used to generate a dimming voltage according to a count of the switching sensing signal; and a phase-controlled non-overlapping driver, used to generate a high side driving signal and a low side driving signal for delivering a lamp current according to the dimming voltage, wherein the dimming voltage is used to generate a phase, and the phase is used to generate the lamp current.

Abstract: An ultra shallow junction (USJ) FET device and method for forming the same with improved control over SDE or LDD doped region interfaces to improve device performance and reliability is provided, the method including providing a semiconductor substrate; forming a gate structure comprising a gate dielectric, an overlying gate electrode, and first offset spacers adjacent either side of the gate electrode; forming at least one doped semiconductor layer comprising dopants over a respective source and drain region adjacent the respective first offset spacers; forming second offset spacers adjacent the respective first offset spacers; and, thermally treating the at least one semiconductor layer to cause out-diffusion of the dopants to form doped regions in the semiconductor substrate.

Abstract: “An active-load dominant circuit for common-mode glitch interference cancellation, biased between a first voltage potential and a second voltage potential with an accompanying common-mode glitch interferer. The active-load dominant circuit includes a pair of pull-up networks and a pair of active-load networks. The common-mode glitch interferer is cancelled out due to a symmetric structure of the pair of pull-up networks. At least one set signal and at least one reset signal are provided to a latch in response to a clock signal or a complemented clock signal. At least one of the set signal and the reset signal can be pulled up to the first voltage potential or pulled down to the second voltage potential. The voltage difference of the set signal and the reset signal is large enough for a latch.

Abstract: An active-load dominant circuit for common-mode glitch interference cancellation, biased between a first voltage potential and a second voltage potential with an accompanying common-mode glitch interferer. The active-load dominant circuit includes a pair of pull-up networks and a pair of active-load networks. The common-mode glitch interferer is cancelled out due to a symmetric structure of the pair of pull-up networks. At least one set signal and at least one reset signal are provided to a latch in response to a clock signal or a complemented clock signal. At least one of the set signal and the reset signal can be pulled up to the first voltage potential or pulled down to the second voltage potential. The voltage difference of the set signal and the reset signal is large enough for a latch.

Abstract: A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking.

Abstract: A transistor having a discontinuous contact etch stop layer comprising: a substrate having a surface, a gate dielectric on said surface of said substrate, a gate electrode on said gate dielectric, a spacer along a sidewall of said gate dielectric and gate electrode, a source and a drain formed on opposite sides, respectively, of said gate dielectric and said gate electrode, the source and drain defining a channel region having a channel length extending substantially from said source to said drain, in the substrate therebetween, and a contact etch stop layer on said gate and said spacers, and said source and drain. The contact etch stop layer is substantially locally continuous in a direction perpendicular to the channel region length and substantially locally discontinuous in a direction parallel to the channel region length.

Abstract: A method of forming fully silicide gates having uniform gate silicide thickness is presented. A gate dielectric is formed over a substrate. A silicon-containing layer is formed over the gate dielectric. A dielectric layer is formed over the silicon-containing layer. A top layer is formed over the dielectric layer. The gate dielectric, the silicon-containing layer, the dielectric layer, and the top layer are patterned into a gate stack. A spacer is formed along an edge of the gate stack. The top layer and the dielectric layer are removed. A metal layer is deposited on the silicon-containing layer and silicided.