Abstract: The present invention relates to a power inductor having a heat dissipating structure formed on the surface thereof, which comprises: at least a conducting wire; and a cladding, made of a magnetic material for wrapping the conductive wire, having the heat dissipating structure of embossed patterns formed on the surface thereof. Preferably, the embossed pattern can be a cone, a cuboid, a column, or the combination thereof. Moreover, the length of any edge or the diameter of any one of the embossed patterns is about 1%˜50% of that of the power inductor, and the height of any one of the embossed patterns is about 1%˜50% of the thickness of the power inductor.

Abstract: This invention discloses a monolithic inductor including a body made by compressing a magnetic powder, a coil positioned in the body, and a permanent magnet positioned in the body and in a magnetic circuit formed by applying current to the coil. The monolithic inductor of this invention includes the magnetic body containing the permanent magnet and the coil. The permanent magnet in the magnetic circuit (path of magnetic flux lines) formed by applying current to the coil generates a reverse-bias magnetic field, thereby increasing the operating range of the magnetic body, the saturation current of the magnetic body, and the rated current of the inductor.

Abstract: A semiconductor product and a method for fabricating the semiconductor product provide a pair of gate electrodes formed with respect to a pair of doped wells within a semiconductor substrate. One of the gate electrodes is formed of a first gate electrode material having a first concentration of an electrically active dopant therein. A second of the gate electrodes is formed of the first gate electrode material having less than the first concentration of the electrically active dopant therein, and formed at least partially as an alloy with a second gate electrode material. The semiconductor product may be formed with enhanced efficiency.

Abstract: The present invention relates to a power inductor having a heat dissipating structure formed on the surface thereof, which comprises: at least a conducting wire; and a cladding, made of a magnetic material for wrapping the conductive wire, having the heat dissipating structure of embossed patterns formed on the surface thereof. Preferably, the embossed pattern can be a cone, a cuboid, a column, or the combination thereof. Moreover, the length of any edge or the diameter of any one of the embossed patterns is about 1%˜50% of that of the power inductor, and the height of any one of the embossed patterns is about 1%˜50% of the thickness of the power inductor.

Abstract: An ultra shallow junction (USJ) FET device and method for forming the same with improved control over SDE or LDD doped region interfaces to improve device performance and reliability is provided, the method including providing a semiconductor substrate; forming a gate structure comprising a gate dielectric, an overlying gate electrode, and first offset spacers adjacent either side of the gate electrode; forming at least one doped semiconductor layer comprising dopants over a respective source and drain region adjacent the respective first offset spacers; forming second offset spacers adjacent the respective first offset spacers; and, thermally treating the at least one semiconductor layer to cause out-diffusion of the dopants to form doped regions in the semiconductor substrate.

Abstract: A transistor having a discontinuous contact etch stop layer comprising: a substrate having a surface, a gate dielectric on said surface of said substrate, a gate electrode on said gate dielectric, a spacer along a sidewall of said gate dielectric and gate electrode, a source and a drain formed on opposite sides, respectively, of said gate dielectric and said gate electrode, the source and drain defining a channel region having a channel length extending substantially from said source to said drain, in the substrate therebetween, and a contact etch stop layer on said gate and said spacers, and said source and drain. The contact etch stop layer is substantially locally continuous in a direction perpendicular to the channel region length and substantially locally discontinuous in a direction parallel to the channel region length.

Abstract: Methods of manufacturing transistor gate electrodes including, in one embodiment, forming a metal layer over first and second regions of a substrate, wherein the first and second regions have different first and second dopant types, respectively. A semiconductor layer is formed over at least a portion of the second region. The metal layer is heated to form a metal gate electrode over the first region, and the metal layer and the semiconductor layer are collectively heated to form a composite metal gate electrode over the second region.

Abstract: A method of forming fully silicide gates having uniform gate silicide thickness is presented. A gate dielectric is formed over a substrate. A silicon-containing layer is formed over the gate dielectric. A dielectric layer is formed over the silicon-containing layer. A top layer is formed over the dielectric layer. The gate dielectric, the silicon-containing layer, the dielectric layer, and the top layer are patterned into a gate stack. A spacer is formed along an edge of the gate stack. The top layer and the dielectric layer are removed. A metal layer is deposited on the silicon-containing layer and silicided.

Abstract: Methods of manufacturing transistor gate electrodes including, in one embodiment, forming a metal layer over first and second regions of a substrate, wherein the first and second regions have different first and second dopant types, respectively. A semiconductor layer is formed over at least a portion of the second region. The metal layer is heated to form a metal gate electrode over the first region, and the metal layer and the semiconductor layer are collectively heated to form a composite metal gate electrode over the second region.

Abstract: A MOSFET includes a gate having a high-k gate dielectric on a substrate and a gate electrode on the gate dielectric. The gate dielectric protrudes beyond the gate electrode. A deep source and drain having shallow extensions are formed on either side of the gate. The deep source and drain are formed by selective in-situ doped epitaxy or by ion implantation and the extensions are formed by selective, in-situ doped epitaxy. The extensions lie beneath the gate in contact with the gate dielectric. The material of the gate dielectric and the amount of its protrusion beyond the gate electrode are selected so that epitaxial procedures and related procedures do not cause bridging between the gate electrode and the source/drain extensions. Methods of fabricating the MOSFET are described.

Abstract: A strained channel transistor is provided. The strained channel transistor comprises a substrate formed of a first material. A source region comprised of a second material is formed in a first recess in the substrate, and a drain region comprised of the second material is formed in a second recess in the substrate. A strained channel region formed of the first material is intermediate the source and drain region. A gate stack formed over the channel region includes a gate electrode overlying a gate dielectric. A gate spacer formed along a sidewall of the gate electrode overlies a portion of at least one of said source region and said drain region. A cap layer may be formed over the second material, and the source and drain regions may be silicided.

Abstract: A ferrite with a high permeability and a high dielectric constant is introduced. Raw material powders, such as TiO2, Fe2O3 and the oxide of Mn, Ni, Cu, Mg, Li or Zn is prepared and combined in the proportion Tix(MFe2O4+2x/y)y, where x+y=1 and 0<×<1. M is any one of a mixture of metals selected from Mn, Ni, Cu, and Zn. The ratio between x and y can be adjusted according to practical needs to obtain ferrites with different permeabilities and dielectric constants. The ferrite can simultaneously be a magnetic material and a dielectric material in an electronic element. This can avoid the possible drawbacks due to sintering of two different materials in the prior art.