Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.

Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.

Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.

Abstract: A therapeutic bra structure includes a bra body having a bra layered member and a side bra layered member on both sides of the bra layered member separately, a fastener assembly or adhesive assembly combined with a distal edge of the side bra layered member and an elastic adjusting assembly having two elastic adjusting layers. Each elastic adjusting layer has an elastic and permeable layered member, and the two elastic adjusting layers are fixed to an inner side of the bra layered member, and an end adhesive assembly is provided at an outer edge of the elastic adjusting layers for the purpose of combining and positioning. This structure allows users to adjust the elasticity and has the effects of healing the wound stably, facilitating the use and installation of a drainage tube or an artificial blood vessel, and ensuring the safety of wearing bra after breast surgery.

Abstract: Disclosed herein are related to a circuit and a method of reading or sensing multiple bits of data stored by a multi-level cell. In one aspect, a first reference circuit is selected from a first set of reference circuits, and a second reference circuit is selected from a second set of reference circuits. Based at least in part on the first reference circuit and the second reference circuit, one or more bits of multiple bits of data stored by a multi-level cell can be determined. According to the determined one or more bits, a third reference circuit from the first set of reference circuits and a fourth reference circuit from the second set of reference circuits can be selected. Based at least in part on the third reference circuit and the fourth reference circuit, additional one or more bits of the multiple bits of data stored by the multi-level cell can be determined.

Abstract: Systems and methods for a bit-cell are presented. The bit-cell comprises a read-port circuit and a write-port circuit. The read-port circuit comprises four transistors, wherein the read-port circuit is activated by a first threshold voltage. The write-port circuit comprises eight transistors, wherein the write-port circuit is activated by a second threshold voltage. The write-port circuit is coupled to the read-port circuit. The first threshold voltage and the second threshold voltage may be different and may be provided by a single supply voltage.

Abstract: Systems and methods for a bit-cell are presented. The bit-cell comprises a read-port circuit and a write-port circuit. The read-port circuit comprises four transistors, wherein the read-port circuit is activated by a first threshold voltage. The write-port circuit comprises eight transistors, wherein the write-port circuit is activated by a second threshold voltage. The write-port circuit is coupled to the read-port circuit. The first threshold voltage and the second threshold voltage may be different and may be provided by a single supply voltage.

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

Abstract: The present invention provides an artificial tooth comprising a plurality of internal crown members, a plurality of connecting rods, at least one external crown member, at least one spring clip. The internal crown members are respectively fitted to a plurality of abutments. Each of the connecting rods connects to at least two of the internal crown members. The external crown member has at least one groove therein, and the groove is formed to correspond to the internal crown members. The spring clip clamps a protrusion block formed on the internal crown members or on an adjacent tooth. Further, the spring clip comprises two spring arms opposite each other, and each of two spring arms has a fixed end and a movable end opposite to fixed end. Each of two spring arms connects to the fixed end and the movable end, and fixed end is fixed inside the internal crown members.

Abstract: Systems and methods for a bit-cell are presented. The bit-cell comprises a read-port circuit and a write-port circuit. The read-port circuit comprises four transistors, wherein the read-port circuit is activated by a first threshold voltage. The write-port circuit comprises eight transistors, wherein the write-port circuit is activated by a second threshold voltage. The write-port circuit is coupled to the read-port circuit. The first threshold voltage and the second threshold voltage may be different and may be provided by a single supply voltage.

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.

Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.

Abstract: A twelve-transistor (12T) memory cell for a memory device that includes a transmission gate, a cross-coupled inverter circuit operably connected to the transmission gate, and a tri-state inverter operably connected to the cross-coupled inverter circuit. The cross-coupled inverter includes another tri-state inverter cross-coupled to an inverter circuit. Various operations for the 12T memory cell, as well as circuitry to perform the operations, are disclosed.

Abstract: A therapeutic bra structure includes a bra body having a bra layered member and a side bra layered member on both sides of the bra layered member separately, a fastener assembly or adhesive assembly combined with a distal edge of the side bra layered member and an elastic adjusting assembly having two elastic adjusting layers. Each elastic adjusting layer has an elastic and permeable layered member, and the two elastic adjusting layers are fixed to an inner side of the bra layered member, and an end adhesive assembly is provided at an outer edge of the elastic adjusting layers for the purpose of combining and positioning. This structure allows users to adjust the elasticity and has the effects of healing the wound stably, facilitating the use and installation of a drainage tube or an artificial blood vessel, and ensuring the safety of wearing bra after breast surgery.

Abstract: A chip package including a lead frame, a first chip, a heat dissipation structure, and an insulating encapsulant is provided. The lead frame includes a chip pad having a first surface and a second surface opposite to the first surface and a lead connected to the chip pad. The first chip is disposed on the first surface of the chip pad and electrically connected to the lead of the lead frame and to the outside of the insulating encapsulant via the lead. The head dissipation structure is disposed on the second surface of the chip pad and includes a thermal interface material layer attached to the second surface. The insulating encapsulant encapsulates the first chip, the heat dissipation structure, and a portion of the lead frame.

Abstract: An optical touch system including an optical touch apparatus and an optical touch stylus is provided. The optical touch apparatus includes a curved operation surface and a plurality of optical sensors. The curved operation surface has a vertex. The optical touch stylus performs a touch operation on the curved operation surface, and has a tip portion for generating a light signal. The optical sensors are arranged on a side of the curved operation surface based on a reference line. The optical sensors are configured to receive the light signal to sense the touch operation of the optical touch stylus performed on the curved operation surface. A surface sag exists between each of the optical sensors and the vertex. A difference between a tip length of the optical touch stylus and a distance of two selected surface sags is not smaller than a region parameter of the optical touch system.

Abstract: A plasma processing method performs an etching process of supplying a fluorine-containing gas into a plasma processing space and etching a target substrate, in which a silicon oxide film or a silicon nitride film is formed on a surface of a metal silicide film, with plasma of the fluorine-containing gas (process S101). Then, the plasma processing method performs a reduction process of supplying a hydrogen-containing gas into the plasma processing space and reducing, with plasma of the hydrogen-containing gas, a metal-containing material deposited on a member, of which a surface is arranged to face the plasma processing space, after the etching process (process S102). Thereafter, the plasma processing method performs a removal process of supplying an oxygen-containing gas into the plasma processing space and removing metal, which is obtained by reducing the metal-containing material in the reduction process, with plasma of the oxygen-containing gas (process S103).

Abstract: An optical touch device and a touch detecting method using the same are provided. The optical touch device is suitable for use with a touch surface and includes a control unit and first to fourth optical capturing units. The first to fourth optical capturing units are disposed on a side of the optical touch device close to the touch surface. The first to fourth optical capturing units are respectively disposed at predetermined distances from the touch surface and are disposed based on predetermined angles. A touch covering area of each of the first to fourth optical capturing units is obtained respectively based on the predetermined distance and the predetermined angle. The touch covering area is positively correlated to the predetermined distance. At least one touch point on the touch surface is calculated by the control unit based on optical sensing information captured by the first to fourth optical capturing units.

Abstract: An optical touch system including an optical touch apparatus and an optical touch stylus is provided. The optical touch apparatus includes a curved operation surface and a plurality of optical sensors. The curved operation surface has a vertex. The optical touch stylus performs a touch operation on the curved operation surface, and has a tip portion for generating a light signal. The optical sensors are arranged on a side of the curved operation surface based on a reference line. The optical sensors are configured to receive the light signal to sense the touch operation of the optical touch stylus performed on the curved operation surface. A surface sag exists between each of the optical sensors and the vertex. A difference between a tip length of the optical touch stylus and a distance of two selected surface sags is not smaller than a region parameter of the optical touch system.