Patents by Inventor Yen-Wen Chen

Yen-Wen Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240139262
    Abstract: The present disclosure relates to a complex probiotic composition and a method for improving exercise performance of a subject with low intrinsic aerobic exercise capacity. The complex probiotic composition, which includes Lactobacillus rhamnosus GKLC1, Bifidobacterium lactis GKK24 and Clostridium butyricum GKB7, administered to the subject with the low intrinsic aerobic exercise capacity in a continuation period, can effectively reduce serum lactic acid and serum urea nitrogen after aerobic exercise, reduce proportion of offal fat and/or increase liver and muscle glycogen contents, thereby being as an effective ingredient for preparation of various compositions.
    Type: Application
    Filed: October 13, 2023
    Publication date: May 2, 2024
    Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shih-Wei LIN, Yen-Po CHEN, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG, You-Shan TSAI, Zi-He WU
  • Patent number: 11968869
    Abstract: An electronic device includes a flexible substrate and a conductive wire. The conductive wire is disposed on the flexible substrate and includes a metal portion and a plurality of openings disposed in the metal portion. The metal portion includes a plurality of extending portions and a plurality of joint portions, and each of the openings is surrounded by two of the plurality of extending portions and two of the plurality of joint portions. A ratio of a sum of widths of the plurality of extending portions to a sum of widths of the plurality of joint portions is in a range from 0.8 to 1.2.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: April 23, 2024
    Assignee: InnoLux Corporation
    Inventors: Ya-Wen Lin, Chien-Chih Chen, Yen-Hsi Tu, Cheng-Wei Chang, Shu-Hui Yang
  • Publication number: 20240088223
    Abstract: In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.
    Type: Application
    Filed: March 24, 2023
    Publication date: March 14, 2024
    Inventors: Shu-Wen SHEN, Yen-Po Lin, Chun-Han Chen
  • Patent number: 11914429
    Abstract: An electronic device includes a host, a display, a sliding plate, and a keyboard. The host has an operating surface. The display is pivoted to the host. The sliding plate is slidably disposed in the host, where the display is mechanically coupled to the sliding plate, and the sliding plate includes a plat portion and a recess portion that are arranged side by side. The keyboard is integrated to the host. The keyboard includes a key structure, where the key structure includes a key cap and a reciprocating element, and the key cap is exposed from the operating surface of the host. The reciprocating element is disposed between the key cap and the sliding plate and has a first end connected to the key cap and a second end contacting the sliding plate. The second end is located on a sliding path of the plat portion and the recess portion.
    Type: Grant
    Filed: March 9, 2023
    Date of Patent: February 27, 2024
    Assignee: Acer Incorporated
    Inventors: Hung-Chi Chen, Shun-Bin Chen, Huei-Ting Chuang, Yen-Chieh Chiu, Yu-Wen Lin, Yen-Chou Chueh, Po-Yi Lee
  • Publication number: 20220361978
    Abstract: An endoscope cleaning device is applied to an endoscope having a main body and a tube body connected to the main body. The endoscope cleaning device includes a frame, a receiving tank for receiving the tube body, a circulating module, and an operating module that is electrically connected to the circulating module. The receiving tank and the operating module are disposed on the frame. The circulating module is connected to a source of first solution supply, a source of second solution supply, and the receiving tank. The operating module is manipulated by a user to control the circulating module to transmit the solution provided by the source of first solution supply and the solution provided by the source of second solution supply to the receiving tank and then to drain the solution in the receiving tank out. A cleaning method of an endoscope by using the endoscope cleaning device is provided.
    Type: Application
    Filed: May 11, 2021
    Publication date: November 17, 2022
    Applicant: ADRONIC ENDOSCOPE CO., LTD.
    Inventors: HSIANG-TE TSENG, YEN-WEN CHEN, SHIH-HONG HUANG
  • Patent number: 11289568
    Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: March 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Wen-Chuan Tai, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Anderson Lin, Fu-Chun Huang, Chun-Ren Cheng, Ivan Hua-Shu Wu, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
  • Publication number: 20210383972
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.
    Type: Application
    Filed: August 25, 2021
    Publication date: December 9, 2021
    Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
  • Patent number: 11107630
    Abstract: Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
  • Patent number: 10693019
    Abstract: Various embodiments of the present application are directed towards a trench capacitor with a high capacitance density. In some embodiments, the trench capacitor overlies the substrate and fills a trench defined by the substrate. The trench capacitor comprises a lower capacitor electrode, a capacitor dielectric layer, and an upper capacitor electrode. The capacitor dielectric layer overlies the lower capacitor electrode and lines the trench. The upper capacitor electrode overlies the capacitor dielectric layer and lines the trench over the capacitor dielectric layer. The capacitor dielectric layer comprises a high ? dielectric material. By using a high ? material for the dielectric layer, the trench capacitor may have a high capacitance density suitable for use with high performance mobile devices.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Jing-Hwang Yang, Ting-Chen Hsu, Felix Ying-Kit Tsui, Yen-Wen Chen
  • Publication number: 20200165083
    Abstract: The disclosure provides a transporting device, a transporting system, and a shelf transporting method. The method includes: estimating a device pose of the transporting device in a specific field; detecting a shelf pose of a shelf located in the specific field; in response to receiving a transporting request for the shelf, setting an entry point associated with the shelf based on the shelf pose of the shelf, and controlling the transporting device to move to the entry point; in response to determining that the transporting device has arrived at the entry point, rotating to align with the shelf, and entering an accommodating space beneath the shelf via an entrance of the shelf; raising a lift bar to dock with the shelf, and moving to transport the shelf.
    Type: Application
    Filed: November 18, 2019
    Publication date: May 28, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Chau-Lin Huang, Yen-Wen Chen, Chun-Ying Yu
  • Patent number: 10605769
    Abstract: A sensing device including a transistor, at least one response electrode, and a receptor is provided. The transistor includes a gate end, a source end, a drain end, and a semiconductor layer. The source end and the drain end are located on the semiconductor layer, and the gate end is located between the source end and the drain end. The at least one response electrode is disposed opposite to the gate end of the transistor and spaced apart from the transistor. The receptor is bonded onto the at least one response electrode. When a voltage is applied to the at least one response electrode, an electric field between the at least one response electrode and the gate end of the transistor is F, and F?1 mV/cm.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: March 31, 2020
    Assignee: National Tsing Hua University
    Inventors: Yu-Lin Wang, Yen-Wen Chen
  • Publication number: 20200098517
    Abstract: Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.
    Type: Application
    Filed: May 21, 2019
    Publication date: March 26, 2020
    Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
  • Publication number: 20200066922
    Abstract: Various embodiments of the present application are directed towards a trench capacitor with a high capacitance density. In some embodiments, the trench capacitor overlies the substrate and fills a trench defined by the substrate. The trench capacitor comprises a lower capacitor electrode, a capacitor dielectric layer, and an upper capacitor electrode. The capacitor dielectric layer overlies the lower capacitor electrode and lines the trench. The upper capacitor electrode overlies the capacitor dielectric layer and lines the trench over the capacitor dielectric layer. The capacitor dielectric layer comprises a high ? dielectric material. By using a high ? material for the dielectric layer, the trench capacitor may have a high capacitance density suitable for use with high performance mobile devices.
    Type: Application
    Filed: August 27, 2018
    Publication date: February 27, 2020
    Inventors: Hsin-Li Cheng, Jyun-Ying Lin, Jing-Hwang Yang, Ting-Chen Hsu, Felix Ying-Kit Tsui, Yen-Wen Chen
  • Publication number: 20200006469
    Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.
    Type: Application
    Filed: May 13, 2019
    Publication date: January 2, 2020
    Inventors: Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Wen-Chuan Tai, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Anderson Lin, Fu-Chun Huang, Chun-Ren Cheng, Ivan Hua-Shu Wu, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
  • Publication number: 20190107507
    Abstract: A sensing device including a transistor, at least one response electrode, and a receptor is provided. The transistor includes a gate end, a source end, a drain end, and a semiconductor layer. The source end and the drain end are located on the semiconductor layer, and the gate end is located between the source end and the drain end. The at least one response electrode is disposed opposite to the gate end of the transistor and spaced apart from the transistor. The receptor is bonded onto the at least one response electrode. When a voltage is applied to the at least one response electrode, an electric field between the at least one response electrode and the gate end of the transistor is F, and F?1 mV/cm.
    Type: Application
    Filed: January 8, 2018
    Publication date: April 11, 2019
    Applicant: National Tsing Hua University
    Inventors: Yu-Lin Wang, Yen-Wen Chen
  • Patent number: 9553243
    Abstract: This disclosure relates to a light-emitting apparatus comprising a submount, a chip carrier formed on the submount, a light-emitting chip formed on the chip carrier, a reflecting cup formed on the submount and enclosing the light-emitting chip and the chip carrier, and a transparent encapsulating material for encapsulating the light-emitting chip.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: January 24, 2017
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Ta-Cheng Hsu, Meng-Lun Tsai, Chih-Chiang Lu, Chien-Yuan Wang, Yen-Wen Chen, Ya-Ju Lee
  • Patent number: 9362456
    Abstract: An optoelectronic semiconductor device includes a substrate, a semiconductor system having an active layer formed on the substrate and an electrode structure formed on the semiconductor system, wherein the layout of the electrode structure having at least a first conductivity type contact zone or a first conductivity type bonding pad, a second conductivity type bonding pad, a first conductivity type extension electrode, and a second conductivity type extension electrode wherein the first conductivity type extension electrode and the second conductivity type extension electrode have three-dimensional crossover, and partial of the first conductivity type extension electrode and the first conductivity type contact zone or the first conductivity type bonding pad are on the opposite sides of the active layer.
    Type: Grant
    Filed: September 24, 2012
    Date of Patent: June 7, 2016
    Assignee: EPISTAR CORPORATION
    Inventors: Wei-Yo Chen, Yen-Wen Chen, Chien-Yuan Wang, Min-Hsun Hsieh, Tzer-Perng Chen
  • Publication number: 20160049444
    Abstract: The application discloses an array-type light-emitting device comprising a substrate, a semiconductor light-emitting array formed on the substrate and emitting a first light with a first spectrum, wherein the semiconductor light-emitting array comprises a first light-emitting unit and a second light-emitting units, a first wavelength conversion layer formed on the first light-emitting unit for converting the first light into a third light with a third spectrum, and a circuit layer connecting the first light-emitting unit and the second light-emitting unit in a connection form to make the first light-emitting and the second light-emitting unit light alternately in accordance with a predetermined clock when driving by a power supply.
    Type: Application
    Filed: October 26, 2015
    Publication date: February 18, 2016
    Inventors: Shu-Ting HSU, Yen-Wen CHEN, Wei-Yo CHEN, Tsung-Xian LEE
  • Publication number: 20150317181
    Abstract: An operating system switching method for use in an electronic device is provided. The method includes the steps of: determining whether the first operating system receives an operating system switching command at time t1; storing first status data to a volatile memory and a non-volatile memory when a first operating system enters a non-operating state from an operating state based on the operating system switching command; writing second status data stored in the non-volatile memory to the volatile memory; and controlling the second operating system to enter the operating state from the non-operating state and recover to the operating status at time t2 based on the second status data stored in the volatile memory, wherein time t2 is earlier than time t1.
    Type: Application
    Filed: April 15, 2015
    Publication date: November 5, 2015
    Inventors: Wei CHIANG, Rung-Lung LIN, Chi-Hsiu KAO, Yen-Wen CHEN
  • Publication number: 20150241243
    Abstract: A method for counting steps and an electronic apparatus are provided. The method includes the following steps: obtaining first three-axis accelerating values of the electronic apparatus; removing a specific ratio of an acceleration of gravity from the first three-axis accelerating values to generate second three-axis accelerating values; calculating inner product values and outer produce values according to the second three-axis accelerating values; determining whether a user of the electronic apparatus is in a walking status; if yes, setting the inner product values as reference values; if no, setting the outer product values as the reference values; calculating a number of steps corresponding to the second three-axis accelerating values according to the reference values.
    Type: Application
    Filed: February 10, 2015
    Publication date: August 27, 2015
    Inventors: Yen-Wen Chen, Rung-Lung Lin