Patents by Inventor Yen-Wen Lu

Yen-Wen Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200026196
    Abstract: Methods of determining, and using, a patterning process model that is a machine learning model. The process model is trained partially based on simulation or based on a non-machine learning model. The training data may include inputs obtained from a design layout, patterning process measurements, and image measurements.
    Type: Application
    Filed: February 20, 2018
    Publication date: January 23, 2020
    Applicant: ASML NETHERLANDE B.V.
    Inventors: Ya LUO, Yu CAO, Jen-Shiang WANG, Yen-Wen LU
  • Publication number: 20200012196
    Abstract: A method including: obtaining a characteristic of a portion of a design layout; determining a characteristic of M3D of a patterning device including or forming the portion; and training, by a computer, a neural network using training data including a sample whose feature vector includes the characteristic of the portion and whose supervisory signal includes the characteristic of the M3D. Also disclosed is a method including: obtaining a characteristic of a portion of a design layout; obtaining a characteristic of a lithographic process that uses a patterning device including or forming the portion; determining a characteristic of a result of the lithographic process; training, by a computer, a neural network using training data including a sample whose feature vector includes the characteristic of the portion and the characteristic of the lithographic process, and whose supervisory signal includes the characteristic of the result.
    Type: Application
    Filed: February 13, 2018
    Publication date: January 9, 2020
    Inventors: Peng LIU, Ya LUO, Yu CAO, Yen-Wen LU
  • Patent number: 10296681
    Abstract: Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: May 21, 2019
    Assignee: ASML Netherlands B.V.
    Inventors: Guangqing Chen, Shufeng Bai, Eric Richard Kent, Yen-Wen Lu, Paul Anthony Tuffy, Jen-Shiang Wang, Youping Zhang, Gertjan Zwartjes, Jan Wouter Bijlsma
  • Publication number: 20190147127
    Abstract: Methods of identifying a hot spot from a design layout or of predicting whether a pattern in a design layout is defective, using a machine learning model. An example method disclosed herein includes obtaining sets of one or more characteristics of performance of hot spots, respectively, under a plurality of process conditions, respectively, in a device manufacturing process; determining, for each of the process conditions, for each of the hot spots, based on the one or more characteristics under that process condition, whether that hot spot is defective; obtaining a characteristic of each of the process conditions; obtaining a characteristic of each of the hot spots; and training a machine learning model using a training set including the characteristic of one of the process conditions, the characteristic of one of the hot spots, and whether that hot spot is defective under that process condition.
    Type: Application
    Filed: April 20, 2017
    Publication date: May 16, 2019
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Jing SU, Yi ZOU, Chenxi LIN, Stefan HUNSCHE, Marinus JOCHEMSEN, Yen-Wen LU, Lin Lee CHEONG
  • Publication number: 20180268093
    Abstract: Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Applicant: ASML Netherlands B.V.
    Inventors: Guangqing CHEN, Shufeng Bai, Eric Richard Kent, Yen-Wen Lu, Paul Anthony Tuffy, Jen-Shiang Wang, Youping Zhang, Gertjan Zwartjes, Jan Wouter Bijlsma
  • Patent number: 10007744
    Abstract: Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: June 26, 2018
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Guangqing Chen, Shufeng Bai, Eric Richard Kent, Yen-Wen Lu, Paul Anthony Tuffy, Jen-Shiang Wang, Youping Zhang, Gertjan Zwartjes, Jan Wouter Bijlsma
  • Publication number: 20180089359
    Abstract: Disclosed herein is a computer-implemented method for determining an overlapping process window (OPW) of an area of interest on a portion of a design layout for a device manufacturing process for imaging the portion onto a substrate, the method including: obtaining a plurality of features in the area of interest; obtaining a plurality of values of one or more processing parameters of the device manufacturing process; determining existence of defects, probability of the existence of defects, or both in imaging the plurality of features by the device manufacturing process under each of the plurality of values; and determining the OPW of the area of interest from the existence of defects, the probability of the existence of defects, or both.
    Type: Application
    Filed: November 22, 2017
    Publication date: March 29, 2018
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Frank Gang CHEN, Joseph Werner DE VOCHT, Yuelin DU, Wanyu LI, Yen-Wen LU
  • Patent number: 9903823
    Abstract: A method to determine an overlay error between a first structure and a second structure, wherein the first structure and second structures are on different layers on a substrate and are imaged onto the substrate by a lithographic process, the method comprising: obtaining an apparent overlay error; obtaining a systematic error caused by a factor other than misalignment of the first and second structures; and determining the overlay error by removing the systematic error from the apparent overlay error. The method may alternatively comprise obtaining apparent characteristics of diffraction orders of diffraction by an overlapping portion of the first and second structures; obtaining corrected characteristics of the diffraction orders; determining the overlay error from the corrected characteristics; and adjusting a characteristic of the lithographic process based on the overlay error.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: February 27, 2018
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Yen-Wen Lu, Jay Jianhui Chen, Wei Liu, Boris Menchtchikov, Jen-Shiang Wang, Te-Chih Huang
  • Publication number: 20170357911
    Abstract: A method to improve a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus, the method including: obtaining a target feature; generating a perturbed target feature from the target feature by applying a perturbation thereto; generating a set of training examples includes the perturbed target feature and an indication as whether the perturbed target feature is deemed the same as the target feature; training a learning model with the set of training examples; classifying features in the portion of the design layout into at least two classes: being deemed the same as the target feature, and being deemed different from the target feature.
    Type: Application
    Filed: November 18, 2015
    Publication date: December 14, 2017
    Applicant: ASML Netherlands B.V.
    Inventors: Xiaofeng LIU, Yen-Wen LU
  • Patent number: 9842186
    Abstract: Disclosed herein is a computer-implemented method for determining an overlapping process window (OPW) of an area of interest on a portion of a design layout for a device manufacturing process for imaging the portion onto a substrate, the method comprising: obtaining a plurality of features in the area of interest; obtaining a plurality of values of one or more processing parameters of the device manufacturing process; determining existence of defects, probability of the existence of defects, or both in imaging the plurality of features by the device manufacturing process under each of the plurality of values; and determining the OPW of the area of interest from the existence of defects, the probability of the existence of defects, or both.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: December 12, 2017
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Frank Gang Chen, Joseph Werner De Vocht, Yuelin Du, Wanyu Li, Yen-Wen Lu
  • Patent number: 9619607
    Abstract: Described herein is a method for obtaining a preferred layout for a lithographic process, the method comprising: identifying an initial layout including a plurality of features; and reconfiguring the features until a termination condition is satisfied, thereby obtaining the preferred layout; wherein the reconfiguring comprises evaluating a cost function that measures how a lithographic metric is affected by a set of changes to the features for a plurality of lithographic process conditions, and expanding the cost function into a series of terms at least some of which are functions of characteristics of the features.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: April 11, 2017
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Jun Tao, Been-Der Chen, Yen-Wen Lu, Jiangwei Li, Min-Chun Tsai, Dong Mao
  • Patent number: 9418194
    Abstract: Described herein is a method of processing a pattern layout for a lithographic process, the method comprising: identifying a feature from a plurality of features of the layout, the feature violating a pattern layout requirement; and reconfiguring the feature, wherein the reconfigured feature still violates the pattern layout requirement, the reconfiguring including evaluating a cost function that measures a lithographic metric affected by a change to the feature and a parameter characteristic of relaxation of the pattern layout requirement.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: August 16, 2016
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Taihui Liu, Been-Der Chen, Yen-Wen Lu
  • Publication number: 20160146740
    Abstract: A method to determine an overlay error between a first structure and a second structure, wherein the first structure and second structures are on different layers on a substrate and are imaged onto the substrate by a lithographic process, the method comprising: obtaining an apparent overlay error; obtaining a systematic error caused by a factor other than misalignment of the first and second structures; and determining the overlay error by removing the systematic error from the apparent overlay error. The method may alternatively comprise obtaining apparent characteristics of diffraction orders of diffraction by an overlapping portion of the first and second structures; obtaining corrected characteristics of the diffraction orders; determining the overlay error from the corrected characteristics; and adjusting a characteristic of the lithographic process based on the overlay error.
    Type: Application
    Filed: November 18, 2015
    Publication date: May 26, 2016
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Yen-Wen Lu, Jay Jianhui Chen, Wei Liu, Boris Menchtchikov, Jen-Shiang Wang, Te-Chih Huang
  • Publication number: 20160140267
    Abstract: Methods and systems for automatically generating robust metrology targets which can accommodate a variety of lithography processes and process perturbations. Individual steps of an overall lithography process are modeled into a single process sequence to simulate the physical substrate processing. That process sequence drives the creation of a three-dimensional device geometry as a whole, rather than “building” the device geometry element-by-element.
    Type: Application
    Filed: November 13, 2015
    Publication date: May 19, 2016
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Guangqing CHEN, Shufeng BAI, Eric Richard KENT, Yen-Wen LU, Paul Anthony TUFFY, Jen-Shiang WANG, Youping ZHANG, Gertjan ZWARTJES, Jan Wouter BIJLSMA
  • Publication number: 20160085905
    Abstract: Disclosed herein is a computer-implemented method for determining an overlapping process window (OPW) of an area of interest on a portion of a design layout for a device manufacturing process for imaging the portion onto a substrate, the method comprising: obtaining a plurality of features in the area of interest; obtaining a plurality of values of one or more processing parameters of the device manufacturing process; determining existence of defects, probability of the existence of defects, or both in imaging the plurality of features by the device manufacturing process under each of the plurality of values; and determining the OPW of the area of interest from the existence of defects, the probability of the existence of defects, or both.
    Type: Application
    Filed: September 22, 2015
    Publication date: March 24, 2016
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Frank Gang CHEN, Joseph Werner DE VOCHT, Yuelin DU, Wanyu LI, Yen-Wen LU
  • Patent number: D744437
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: December 1, 2015
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yen-Wen Lu, Chia-Chen Yang
  • Patent number: D758376
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: June 7, 2016
    Assignee: COMPAL ELECTRONICS, INC.
    Inventor: Yen-Wen Lu
  • Patent number: D760233
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: June 28, 2016
    Assignee: COMPAL ELECTRONICS, INC.
    Inventor: Yen-Wen Lu
  • Patent number: D763813
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: August 16, 2016
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Yen-Wen Lu, Kuei-Min Pan
  • Patent number: D782493
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: March 28, 2017
    Assignee: COMPAL ELECTRONICS, INC.
    Inventor: Yen-Wen Lu