Patents by Inventor Yeong-E Chen

Yeong-E Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240136308
    Abstract: An embodiment of the disclosure provides an electronic assembly including a stacked structure, a first integrated circuit, a first passive component, and a first electrode. The stacked structure comprises a plurality of insulating layers and a plurality of conductive layers. The first passive component is disposed between the stacked structure and the first integrated circuit. The first electrode is disposed between the stacked structure and the first passive component. The first passive component is electrically connected to the stacked structure through the first electrode.
    Type: Application
    Filed: January 1, 2024
    Publication date: April 25, 2024
    Applicant: Innolux Corporation
    Inventors: Yeong-E Chen, Wei-Hsuan Chen, Chun-Yuan Huang
  • Publication number: 20240105697
    Abstract: An electronic device is provided. The electronic device includes a circuit structure layer, an insulation layer, a function element and a protection layer. The circuit structure layer has a first side and a second side opposite to the first side. The insulation layer is disposed on the first side and contacts the circuit structure layer. The function element is disposed on the second side of the circuit structure layer. The protection layer exposes a surface of at least one function element and the surface is away from the circuit layer.
    Type: Application
    Filed: December 7, 2023
    Publication date: March 28, 2024
    Applicant: Innolux Corporation
    Inventor: Yeong-E Chen
  • Patent number: 11901315
    Abstract: An embodiment of the disclosure provides a package device including a redistribution layer, an integrated passive device layer, a first port, and a second port. The integrated passive device layer contacts the redistribution layer. The integrated passive device layer has at least one capacitor. The at least one capacitor includes a first capacitor and a second capacitor. The first port is electrically connected to the first capacitor and the second capacitor. The second port is provided opposite to the first port. The second port is electrically connected to the first capacitor and the second capacitor. The first port and the second port have the same resistance.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: February 13, 2024
    Assignee: Innolux Corporation
    Inventors: Yeong-E Chen, Wei-Hsuan Chen, Chun-Yuan Huang
  • Publication number: 20240047633
    Abstract: An electronic device and a manufacturing method thereof are provided. The electronic device includes a substrate, a first metal layer, a first insulating layer, a second metal layer, and a second insulating layer. The first metal layer is disposed on the substrate and configured to transmit a ground signal. The first insulating layer is disposed on the first metal layer and includes at least one first opening. The second metal layer is disposed on the first insulating layer and electrically connected to the first metal layer through the at least one first opening. The second insulating layer is disposed on the second metal layer and includes at least one second opening. In the top view direction, the at least one first opening is separated from the at least one second opening. The electronic device in the embodiments of the disclosure and the manufacturing method thereof may improve the process yield.
    Type: Application
    Filed: July 6, 2023
    Publication date: February 8, 2024
    Applicant: Innolux Corporation
    Inventors: Yi-Hung Lin, Yeong-E Chen, Yan-Zheng Wu
  • Publication number: 20240023235
    Abstract: The present disclosure provides a package device including a redistribution layer. The redistribution layer includes a first dielectric layer, a conductive layer, and a second dielectric layer, and the conductive layer is disposed between the first dielectric layer and the second dielectric layer, wherein the redistribution layer has a test mark, the test mark includes a conductive pattern formed of the conductive layer, the conductive pattern includes a center portion and a plurality of extension portions, and the plurality of extension portions are respectively connected to the center portion.
    Type: Application
    Filed: September 27, 2023
    Publication date: January 18, 2024
    Applicant: InnoLux Corporation
    Inventors: Yeong-E CHEN, Cheng-En CHENG, Yu-Ting LIU
  • Publication number: 20240006249
    Abstract: The present disclosure provides an electronic device including a redistribution layer, a plurality of passive components, and an electronic component. The redistribution layer includes a first insulating layer, a second insulating layer, and a plurality of traces electrically connected to each other through a first opening of the first insulating layer and a second opening of the second insulating layer, wherein the first insulating layer has a first side away from the second insulating layer, and the second insulating layer has a second side away from the first insulating layer. The passive components are disposed on the first side. The electronic component is disposed on the second side. The plurality of passive components are electrically connected to the electronic component through the plurality of traces.
    Type: Application
    Filed: September 19, 2023
    Publication date: January 4, 2024
    Applicant: InnoLux Corporation
    Inventors: Yeong-E CHEN, Kuang-Chiang HUANG, Yu-Ting LIU, Yi-Hung LIN, Cheng-En CHENG
  • Patent number: 11812549
    Abstract: A package device and a manufacturing method thereof are provided. The package device includes a redistribution layer. The redistribution layer includes a first dielectric layer, a conductive layer, and a second dielectric layer, and the conductive layer is disposed between the first dielectric layer and the second dielectric layer, wherein the redistribution layer has a test mark, the test mark includes a conductive pattern formed of the conductive layer, the conductive pattern includes a center portion and a plurality of extension portions, and the plurality of extension portions are respectively connected to the center portion.
    Type: Grant
    Filed: January 10, 2023
    Date of Patent: November 7, 2023
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Cheng-En Cheng, Yu-Ting Liu
  • Patent number: 11798853
    Abstract: The present disclosure provides a manufacturing method of a package device, which includes providing a carrier substrate, a first conductive layer, and a release layer, where the carrier substrate has a device region and a peripheral region, and the first conductive layer and the release layer are disposed on the carrier substrate. The method further includes forming a second conductive layer on the release layer in the device region, where at least one of the first and second conductive layers includes a first pad in the peripheral region. The second conductive layer includes a second pad electrically connected to the first pad through the first conductive layer. The method also includes performing an inspection step to provide an input signal to one of the first and second pads, and to receive an output signal from another of the first and second pads.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: October 24, 2023
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Kuang-Chiang Huang, Yu-Ting Liu, Yi-Hung Lin, Cheng-En Cheng
  • Patent number: 11789066
    Abstract: A method for manufacturing an electronic device includes the following steps. A substrate including a first region and a second region is provided. A seed layer is formed on the substrate. A circuit structure layer is formed on the seed layer, and the circuit structure layer has a plurality of first circuit structures disposed on the first region and a plurality of second circuit structures disposed on the second region. The first circuit structures and the second circuit structures are electrically connected through the seed layer. A circuit test process is performed and includes applying a predetermined voltage to the second circuit structures to test the first circuit structures to determine whether the first circuit structures are normal or not.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: October 17, 2023
    Assignee: Innolux Corporation
    Inventor: Yeong-E Chen
  • Patent number: 11776914
    Abstract: A package device is provided and includes a redistribution layer. The redistribution layer includes a first dielectric layer, a second dielectric layer, and a conductive layer. The second dielectric layer is disposed on the first dielectric layer, and the second dielectric layer includes a dielectric pattern. The conductive layer is disposed between the first dielectric layer and the second dielectric layer, and the conductive layer includes a first conductive pattern. The dielectric pattern has a through hole, and in a top view of the package device, the first conductive pattern and the through hole are overlapped with each other.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: October 3, 2023
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Cheng-En Cheng, Yu-Ting Liu
  • Patent number: 11769685
    Abstract: A manufacturing method of a semiconductor package is provided. The manufacturing method includes the following. A plurality of semiconductor components are provided. Each semiconductor component has at least one conductive bump. A substrate is provided. The substrate has a plurality of conductive pads. A transfer device is provided. The transfer device transfers the semiconductor components onto the substrate. A heating device is provided. The heating device heats or pressurizes at least two semiconductor components. During transferring of the semiconductor components to the substrate, the at least one conductive bump of each semiconductor component is docked to a corresponding one of the conductive pads.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: September 26, 2023
    Assignee: Innolux Corporation
    Inventors: Cheng-Chi Wang, Wen-Hsiang Liao, Yeong-E Chen, Hung-Sheng Chou, Cheng-En Cheng
  • Publication number: 20230290764
    Abstract: An electronic device is provided. The electronic device includes a circuit structure layer, a package structure, and an electronic element. The circuit structure layer includes a circuit layer and a plurality of first conductive pads. The package structure is disposed on the circuit structure layer. The electronic element is embedded in the package structure. The electronic element is electrically connected to the circuit layer through the plurality of first conductive pads. A thickness of the package structure is greater than or equal to 1.5 times a thickness of the electronic element.
    Type: Application
    Filed: May 17, 2023
    Publication date: September 14, 2023
    Applicant: Innolux Corporation
    Inventor: Yeong-E Chen
  • Publication number: 20230245949
    Abstract: An electronic device is disclosed. The electronic device includes a circuit layer, an electronic element and a thermal conducting element. The electronic element is disposed on the circuit layer and electrically connected to the circuit layer. The thermal conducting element is disposed between the circuit layer and the electronic element. The thermal conducting element is used for performing heat exchange with the electronic element.
    Type: Application
    Filed: August 29, 2022
    Publication date: August 3, 2023
    Applicant: InnoLux Corporation
    Inventors: Chin-Lung TING, Chung-Kuang WEI, Cheng-Chi WANG, Yeong-E CHEN, Yi-Hung LIN
  • Patent number: 11694999
    Abstract: An electronic device and a fabrication method thereof are provided. The electronic device includes a circuit structure layer, a package structure, an electronic element, and a plurality of function elements. The circuit structure layer has a first side and a second side opposite to the first side. The package structure is disposed on the first side of the circuit structure layer. The electronic element is embedded or encapsulated in the package structure. The function elements are disposed on the second side of the circuit structure layer. The function elements are electrically connected to the electronic element through the circuit structure layer. The electronic device provided by the disclosure exhibits borderless design or has a large function region.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: July 4, 2023
    Assignee: Innolux Corporation
    Inventor: Yeong-E Chen
  • Publication number: 20230095239
    Abstract: The present disclosure discloses a method for manufacturing an electronic device, including: setting a basic working area; a photoresist coating process; a development process; an etching process; an exposure process; a metal plating process; and a polishing process, wherein the photoresist coating process, the development process, the etching process, the exposure process, the metal plating process and the polishing process respectively have a maximum optimized process area, and a smallest one of the maximum optimized process areas is selected as the basic working area.
    Type: Application
    Filed: December 5, 2022
    Publication date: March 30, 2023
    Applicant: InnoLux Corporation
    Inventors: Cheng-Chi WANG, Yeong-E CHEN, Cheng-En CHENG
  • Publication number: 20230090376
    Abstract: An electronic component and a manufacturing method thereof are provided. The electronic component includes a structure member and a connecting member. The structure member includes at least one working unit. The at least one working unit is disposed in a first region. The connecting member is disposed on the structure member and includes a second region. The second region is overlapped with the first region, and a metal density of the second region is less than a metal density of the first region. The electronic component and the manufacturing method thereof of the embodiment of the disclosure include the effect of improving the reliability or quality of the electronic component.
    Type: Application
    Filed: November 10, 2021
    Publication date: March 23, 2023
    Applicant: Innolux Corporation
    Inventors: Yeong-E Chen, Yi-Hung Lin, Cheng-En Cheng, Wen-Hsiang Liao, Cheng-Chi Wang
  • Publication number: 20230077312
    Abstract: The application relates to a method for manufacturing an electronic device, and in particular, to a method for manufacturing an electronic device with a carrier substrate. The method includes: providing a carrier; forming a first base layer on the carrier; and forming working units on the first base layer. The working units are spaced apart from one another.
    Type: Application
    Filed: October 22, 2021
    Publication date: March 9, 2023
    Inventors: Yeong-E CHEN, Cheng-En CHENG, Yu-Ting LIU, Cheng-Chi WANG
  • Patent number: 11582865
    Abstract: A package device and a manufacturing method thereof are provided. The package device includes a redistribution layer including a first dielectric layer, a conductive layer, and a second dielectric layer. The conductive layer is disposed between the first dielectric layer and the second dielectric layer. The redistribution layer has a test mark, the test mark includes a plurality of conductive patterns formed of the conductive layer, and the conductive patterns are arranged in a ring shape.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: February 14, 2023
    Assignee: InnoLux Corporation
    Inventors: Yeong-E Chen, Cheng-En Cheng, Yu-Ting Liu
  • Publication number: 20230038309
    Abstract: A package device is provided and includes a first circuit layer, a first isolation layer, and a first de-warpage layer. The first circuit layer and the first isolation layer are stacked on each other. At least a portion of the first de-warpage layer is disposed between the first circuit layer and the first isolation layer.
    Type: Application
    Filed: May 4, 2022
    Publication date: February 9, 2023
    Applicant: InnoLux Corporation
    Inventors: Yi-Hung LIN, Chun-Hung LAI, Yeong-E CHEN, Chuan-Ming YEH, Ching-Wei CHEN
  • Patent number: 11551970
    Abstract: The present disclosure discloses a method for manufacturing an electronic device, including: setting a basic working area; providing a supporting platform having a plurality of vacuum valves; disposing a substrate on the supporting platform; applying vacuum attraction to a portion of the substrate through a portion of the plurality of vacuum valves, wherein the portion of the substrate corresponding to the vacuum attraction is defined as an attracted region; and performing an exposure on a portion of the attracted region, wherein an area of the attracted region is larger than the basic working area and smaller than an area of the supporting platform.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: January 10, 2023
    Assignee: InnoLux Corporation
    Inventors: Cheng-Chi Wang, Yeong-E Chen, Cheng-En Cheng