Patents by Inventor Yeong-E Chen

Yeong-E Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200396835
    Abstract: An electronic device is provided. The electronic device includes: a substrate, wherein the substrate has a normal direction; a first bonding pad and a second bonding pad disposed side by side on the substrate. The first bonding pad includes a first conductive layer and a second conductive layer, and the first conductive layer is adjacent to the second conductive layer. The second bonding pad includes a third conductive layer, the third conductive layer is adjacent to the second conductive layer, and in the normal direction, a distance between a bottom surface of the third conductive layer and the substrate is different than a distance between a bottom surface of the second conductive layer and the substrate. Viewed from the normal direction of the substrate, at least part of the second conductive layer is between the first conductive layer and the third conductive layer.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 17, 2020
    Inventors: Yu-Ting LIU, Yeong-E CHEN, Chean KEE
  • Patent number: 6433485
    Abstract: An apparatus and method of testing an organic light emitting diode array are disclosed. A current meter and voltage source are serially connected between a common line and power supply line shared by any pixel unit. Specific logic values are sequentially written to the pixel units via signal lines and the current readings corresponding the pixel units are taken by the current meter. Whether the pixel units are defective can be determined according to the current readings. The defective type of a pixel units can be determined according to the current reading corresponding to the defective pixel unit and the current readings corresponding the other perfect pixel units.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: August 13, 2002
    Assignee: Industrial Technology Research Institute
    Inventors: Ya-Hsiang Tai, Yeong-E Chen
  • Publication number: 20020014851
    Abstract: An apparatus and method of testing an organic light emitting diode array are disclosed. A current meter and voltage source are serially connected between a common line and power supply line shared by any pixel unit. Specific logic values are sequentially written to the pixel units via signal lines and the current readings corresponding the pixel units are taken by the current meter. Whether the pixel units are defective can be determined according to the current readings. The defective type of a pixel units can be determined according to the current reading corresponding to the defective pixel unit and the current readings corresponding the other perfect pixel units.
    Type: Application
    Filed: April 5, 2001
    Publication date: February 7, 2002
    Inventors: Ya-Hsiang Tai, Yeong-E Chen
  • Patent number: 6323034
    Abstract: A thin film transistor design is described which is not subject to either dark or photo current leakage. The process to manufacture this device begins with the formation of a gate electrode on a transparent substrate followed by its over coating with layers of gate insulation, undoped amorphous silicon, doped amorphous silicon, and a second layer of chromium. The chromium and amorphous silicon layers are then patterned and etched to form a channel pedestal. In a key feature of the invention the vertical side walls of this pedestal are then given a protective coating of oxide or nitride, forming spacers. This is then followed by the deposition of second level metal which is etched to form source and drain electrodes with a suitable gap between them.
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: November 27, 2001
    Assignee: Industrial Technology Research Institute
    Inventors: Yeong-E Chen, Jr-Hong Chen, Ya-Hsiang Tai
  • Patent number: 6071762
    Abstract: A process for manufacturing a TFT without the use of ion implantation is described. Instead, heavily doped layers of amorphous silicon are used as diffusion sources. Two embodiments of the invention are described. In the first embodiment the gate pedestal is deposited first, followed by gate oxide and an amorphous layer of undoped silicon. This is followed by the layer of heavily doped amorphous silicon which is subjected to a relatively low energy laser scan which drives in a small amount of dopant and converts it to N-. After the N+ layer has been patterned and etched to form source and drain electrodes, a second, higher energy, laser scan is given. This brings the source and drain very close to, but not touching, the channel, resulting in an LDD type of structure. In the second embodiment a layer of intrinsic polysilicon is used for the channel. It is covered with a layer of gate oxide and a metallic gate pedestal.
    Type: Grant
    Filed: November 16, 1998
    Date of Patent: June 6, 2000
    Assignee: Industrial Technology Research Institute
    Inventors: Hong-Woei Wu, Yeong-E Chen, Gwo-Long Lin