Patents by Inventor Yervant Zorian

Yervant Zorian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10789398
    Abstract: A method for determining redundancy usage rate from a group of memory parameters and a memory yield of a System on a Chip (SoC), using the probabilistic redundancy usage rate and using that rate to calculate an optimal RSMA size. An SoC is then fabricated with the optimal RSMA size.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: September 29, 2020
    Assignee: Synopsys, Inc.
    Inventors: Suren Martirosyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Publication number: 20190035484
    Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.
    Type: Application
    Filed: September 28, 2018
    Publication date: January 31, 2019
    Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Patent number: 10192635
    Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 29, 2019
    Assignee: Synopsys, Inc.
    Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Patent number: 10115477
    Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: October 30, 2018
    Assignee: Synopsys, Inc.
    Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Publication number: 20180130546
    Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.
    Type: Application
    Filed: September 28, 2017
    Publication date: May 10, 2018
    Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Publication number: 20180129769
    Abstract: A method for determining redundancy usage rate from a group of memory parameters and a memory yield of a System on a Chip (SoC), using the probabilistic redundancy usage rate and using that rate to calculate an optimal RSMA size. An SoC is then fabricated with the optimal RSMA size.
    Type: Application
    Filed: August 23, 2017
    Publication date: May 10, 2018
    Inventors: Suren Martirosyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Patent number: 9831000
    Abstract: An integrated circuit includes a memory and a memory test circuit, which when invoked to test the memory, is configured to generate one or more March tests applied to the memory. The memory test circuit is further configured to construct a table including a first index, a second index, and a first March test of the one or more March tests. The first index is associated with one or more families each characterized by a different length of the one or more March tests. The second index is associated with one or more mechanisms each characterized by a different property of the one or more March tests. The memory test circuit is further configured to generate a second March test from the first March test.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: November 28, 2017
    Assignee: SYNOPSYS, INC.
    Inventors: Aram Hakhumyan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
  • Patent number: 9541591
    Abstract: A fully-digital probabilistic measurement methodology in which a periodic signal generated on an IC device is sampled multiple times during a test period, with the asserted/de-asserted state of the periodic signal determined during each sampling event. A statistically significant number of sampling events are executed according to a reference signal frequency that is uncorrelated to the IC's system clock, whereby each successive sampling event involves detecting an essentially random associated phase of the periodic signal such that the probability of detecting an asserted state during any given sampling event is proportional to the duty cycle of the periodic signal. A first count value records the number of sampling events in which the periodic signal is asserted, and a second count value records the total number of sampling events performed, whereby a ratio of these two count values provides a statistical measurement of the periodic signal's duty cycle.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: January 10, 2017
    Assignee: Synopsys, Inc.
    Inventors: Karen Darbinyan, Yervant Zorian, Arun Kumar, Mher Mkhoyan
  • Patent number: 9514258
    Abstract: A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy between the physical bit patterns and the logical bit patterns. The strap distribution information and the address scrambling information are combined into the memory structural model used for designing an efficient test and repair engine.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: December 6, 2016
    Assignee: Synopsys, Inc.
    Inventors: Karen Amirkhanyan, Karen Darbinyan, Arman Davtyan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
  • Patent number: 9336342
    Abstract: A memory hard macro designed to support multiple design for test (DFT) techniques having signal paths associated with the DFT techniques and the functional operation of the memory instance that share logic devices or components. The memory hard macro includes a functional input port and a functional output port, forming a functional memory data path, which includes input latches from the memory instance. The memory hard macro also includes a scan input port and a scan output port, forming a scan data path, which includes input latches from the array of data buffer circuits and output latches from the array of sense amplifiers. The memory hard macro further includes a BIST input port and a BIST output port, forming a BIST data path, which includes at least one input latch from the array of data buffer circuits and at least one output latch from the array of sense amplifiers.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 10, 2016
    Assignee: Synopsys, Inc.
    Inventors: Yervant Zorian, Karen Darbinyan, Gevorg Torjyan
  • Publication number: 20160041212
    Abstract: A fully-digital probabilistic measurement methodology in which a periodic signal generated on an IC device is sampled multiple times during a test period, with the asserted/de-asserted state of the periodic signal determined during each sampling event. A statistically significant number of sampling events are executed according to a reference signal frequency that is uncorrelated to the IC's system clock, whereby each successive sampling event involves detecting an essentially random associated phase of the periodic signal such that the probability of detecting an asserted state during any given sampling event is proportional to the duty cycle of the periodic signal. A first count value records the number of sampling events in which the periodic signal is asserted, and a second count value records the total number of sampling events performed, whereby a ratio of these two count values provides a statistical measurement of the periodic signal's duty cycle.
    Type: Application
    Filed: August 10, 2015
    Publication date: February 11, 2016
    Inventors: Karen Darbinyan, Yervant Zorian, Arun Kumar, Mher Mkhoyan
  • Patent number: 9053050
    Abstract: A desirable number of segments for a multi-segment single error correcting (SEC) coding scheme is determined based on scrambling information for a memory. The desirable number of segments can be the minimum number of segments required to satisfy a masked write segmentation requirement and a multi-bit upset size requirement. In one aspect, the memory scrambling information can specify the different scrambling techniques employed by the memory (e.g., Input-Output (IO) cell scrambling, column scrambling, column twisting, strap distribution, etc.). Based on the scrambling information, a mapping between the logical structure and physical layout for the memory can be derived. The mapping can be used to determine the least number of segments needed to satisfy the masked write requirement and the multi-bit upset size requirement.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: June 9, 2015
    Assignee: Synopsys, Inc.
    Inventors: Hayk Grigoryan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
  • Publication number: 20140380107
    Abstract: An integrated circuit includes a memory and a memory test circuit, which when invoked to test the memory, is configured to generate one or more March tests applied to the memory. The memory test circuit is further configured to construct a table including a first index, a second index, and a first March test of the one or more March tests. The first index is associated with one or more families each characterized by a different length of the one or more March tests. The second index is associated with one or more mechanisms each characterized by a different property of the one or more March tests. The memory test circuit is further configured to generate a second March test from the first March test.
    Type: Application
    Filed: September 12, 2014
    Publication date: December 25, 2014
    Inventors: Aram Hakhumyan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
  • Patent number: 8850277
    Abstract: A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.
    Type: Grant
    Filed: July 15, 2011
    Date of Patent: September 30, 2014
    Assignee: Synopsys, Inc.
    Inventors: Karen Amirkhanyan, Hayk Grigoryan, Gurgen Harutyunyan, Tatevik Melkumyan, Samvel Shoukourian, Alex Shubat, Valery Vardanian, Yervant Zorian
  • Publication number: 20130346056
    Abstract: A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy between the physical bit patterns and the logical bit patterns. The strap distribution information and the address scrambling information are combined into the memory structural model used for designing an efficient test and repair engine.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 26, 2013
    Applicant: SYNOPSYS, INC.
    Inventors: Karen Amirkhanyan, Karen Darbinyan, Arman Davtyan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
  • Publication number: 20130145119
    Abstract: A desirable number of segments for a multi-segment single error correcting (SEC) coding scheme is determined based on scrambling information for a memory. The desirable number of segments can be the minimum number of segments required to satisfy a masked write segmentation requirement and a multi-bit upset size requirement. In one aspect, the memory scrambling information can specify the different scrambling techniques employed by the memory (e.g., Input-Output (IO) cell scrambling, column scrambling, column twisting, strap distribution, etc.). Based on the scrambling information, a mapping between the logical structure and physical layout for the memory can be derived. The mapping can be used to determine the least number of segments needed to satisfy the masked write requirement and the multi-bit upset size requirement.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Applicant: Synopsys, Inc.
    Inventors: Hayk Grigoryan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
  • Publication number: 20130080847
    Abstract: A memory hard macro designed to support multiple design for test (DFT) techniques having signal paths associated with the DFT techniques and the functional operation of the memory instance that share logic devices or components. The memory hard macro includes a functional input port and a functional output port, forming a functional memory data path, which includes input latches from the memory instance. The memory hard macro also includes a scan input port and a scan output port, forming a scan data path, which includes input latches from the array of data buffer circuits and output latches from the array of sense amplifiers. The memory hard macro further includes a BIST input port and a BIST output port, forming a BIST data path, which includes at least one input latch from the array of data buffer circuits and at least one output latch from the array of sense amplifiers.
    Type: Application
    Filed: September 23, 2011
    Publication date: March 28, 2013
    Applicant: SYNOPSYS, INC.
    Inventors: Yervant Zorian, Karen Darbinyan, Gevorg Torjyan
  • Patent number: 8359553
    Abstract: A method and apparatus are described in which an optimal configuration of memory instances is determined. The optimal configuration of memory instances to be fabricated with built-in repair capacity and memory instances that are non-repairable may provide a maximum number of good chip dies per wafer. An amount of memory instances to be fabricated with built-in repair capacity as well as a remaining amount of memory instances to be fabricated without any built-in repair components in the integrated circuit design is determined relative to achieving the maximum number of good chip dies per wafer for a given defect density and wafer area. The amount of good dies produced per fabricated wafer for a populated amount of memories with built-in repair components is determined to be between an amount established by a minimum limit for the die area up to the amount established by a maximum limit for the die area.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: January 22, 2013
    Assignee: Synopsys, Inc.
    Inventors: Karen Aleksanyan, Valery Vardanian, Yervant Zorian
  • Publication number: 20130019132
    Abstract: A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.
    Type: Application
    Filed: July 15, 2011
    Publication date: January 17, 2013
    Applicant: SYNOPSYS INC.
    Inventors: Karen AMIRKHANYAN, Hayk Grigoryan, Gurgen Harutyunyan, Tatevik Melkumyan, Samvel Shoukourian, Alex Shubat, Valery Vardanian, Yervant Zorian
  • Publication number: 20130019130
    Abstract: Testing electronic memories based on fault and test algorithm periodicity. A processor unit for testing an electronic memory includes a built-in self-test (BIST) finite state machine, an address generator, a data generator, a test algorithm generation unit, a programmable test algorithm register, and a test algorithm register control unit. A memory wrapper unit for testing an electronic memory includes an operation decoder, a data comparator, and an electronic memory under test. The method includes constructing a fault periodic table having columns corresponding with test mechanisms, and rows corresponding with fault families. A first March test sequence and second March test sequence are selected according to respective fault families and test mechanisms, and applied to an electronic memory. The electronic memory under test is determined to be one of acceptable and unacceptable based on results of the first March test sequence and the second March test sequence.
    Type: Application
    Filed: July 15, 2011
    Publication date: January 17, 2013
    Applicant: SYNOPSYS INC.
    Inventors: Aram HAKHUMYAN, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian