Patents by Inventor Yervant Zorian

Yervant Zorian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12266413
    Abstract: A method for testing a chip includes writing, by a built-in self-test (BIST) circuit of the chip, a first row of a memory of the chip with a first set of values and reading, by the BIST circuit, a second row of the memory a first plurality of times. The second row is adjacent to the first row. The method also includes reading, by the BIST circuit, the first row to extract a second set of values from the first row and based on determining that at least one of the second set of values differs from a corresponding one of the first set of values, designating the first row as a vulnerable row.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: April 1, 2025
    Assignee: Synopsys, Inc.
    Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Arun Kumar, Yervant Zorian
  • Publication number: 20250078882
    Abstract: An integrated circuit includes delay monitors that monitor the delays of data signals from the digital circuitry by generating pulses having widths determined by the delays. In some embodiments, the delay monitor is implemented as a digital circuit that includes a pulse generator and an event generator. The delay monitor receives a data signal and a clock signal used to clock the data signal. The pulse generator generates pulses from the received data and clock signals, where the widths of the pulses are determined by a delay of the data signal relative to the clock signal. The event generator generates events that are distributed in time relative to the clock signal. As a result, the delay is estimable based on an overlap between the events and the pulses.
    Type: Application
    Filed: September 6, 2023
    Publication date: March 6, 2025
    Inventors: Karen Darbinyan, Yervant Zorian, Grigor Khachatryan, Karen Melkonyan
  • Patent number: 12094548
    Abstract: Methods for diagnosing faults in memory periphery circuitry, computer readable media, and a test device for the same are provided. In one example, method is provided that includes receiving, at a test device, a first test syndrome from a memory device, the first test syndrome corresponds to a first test process executed by the memory device, wherein the memory device comprises a memory array and peripheral circuitry, and wherein the first test process is associated with a first circuit element of the peripheral circuitry; determining, by a processing device of the test device, a first fault associated with the first circuit element based on the first test syndrome; and diagnosing, by the processing device, the first fault to determine positional information of the first fault, the positional information is associated with the first circuit element.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: September 17, 2024
    Assignee: Synopsys, Inc.
    Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian
  • Patent number: 12002530
    Abstract: A memory transparent in-system built-in self-test may include performing in-system testing on subsets of memory cells over one or more test intervals of one or more test sessions. A test interval may include copying contents of a subset of memory cells to a register(s), writing test data (e.g., a segment of a pattern) to the subset of memory cells, reading back contents of the subset of memory cells, and restoring the content from the register(s) to the subset of memory cells. In-system testing may be performed on overlapping sets of memory cells. In-system testing may be performed on successive subsets of memory cells within a row (i.e., fast column addressing) and/or within a column (fast column addressing). In-system testing may be performed on sets of m blocks of memory cells during respective test intervals. The number of m blocks tested per interval may be configurable/selectable.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: June 4, 2024
    Assignee: Synopsys, Inc.
    Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Publication number: 20240096435
    Abstract: A method for testing a chip includes writing, by a built-in self-test (BIST) circuit of the chip, a first row of a memory of the chip with a first set of values and reading, by the BIST circuit, a second row of the memory a first plurality of times. The second row is adjacent to the first row. The method also includes reading, by the BIST circuit, the first row to extract a second set of values from the first row and based on determining that at least one of the second set of values differs from a corresponding one of the first set of values, designating the first row as a vulnerable row.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Inventors: Grigor TSHAGHARYAN, Gurgen HARUTYUNYAN, Arun KUMAR, Yervant ZORIAN
  • Publication number: 20230140090
    Abstract: A memory transparent in-system built-in self-test may include performing in-system testing on subsets of memory cells over one or more test intervals of one or more test sessions. A test interval may include copying contents of a subset of memory cells to a register(s), writing test data (e.g., a segment of a pattern) to the subset of memory cells, reading back contents of the subset of memory cells, and restoring the content from the register(s) to the subset of memory cells. In-system testing may be performed on overlapping sets of memory cells. In-system testing may be performed on successive subsets of memory cells within a row (i.e., fast column addressing) and/or within a column (fast column addressing). In-system testing may be performed on sets of m blocks of memory cells during respective test intervals. The number of m blocks tested per interval may be configurable/selectable.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 4, 2023
    Inventors: Grigor TSHAGHARYAN, Gurgen HARUTYUNYAN, Samvel SHOUKOURIAN, Yervant ZORIAN
  • Patent number: 11527298
    Abstract: An on-chip memory diagnostic (OCMD) circuit may instruct a set of built-in self-test (BIST) engines to execute BIST on memories associated with the set of BIST engines. Next, results of executing BIST on the memories may be received from the set of BIST engines. A set of memory failures may then be identified in the memories based on the results. Next, one or more BIST engines in the set of BIST engines may be instructed to collect diagnostic data for each memory failure. A set of diagnostic data may then be received for the set of memory failures. Next, the set of diagnostic data may be stored in an on-chip data container. The set of diagnostic data may then be provided via a communication channel.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: December 13, 2022
    Assignee: Synopsys, Inc.
    Inventors: Karen Darbinyan, Tatevik Melkumyan, Yervant Zorian
  • Patent number: 11023310
    Abstract: A system including a user interface, a memory, and a processor configured to perform operations including receiving memory scrambling information including address scrambling information and data scrambling information, and associating one or more address bus bits of a plurality of address bus bits with an address grouping of a plurality of address groupings based on the address scrambling information is disclosed. In an embodiment, the address grouping corresponds to at least one address segment of a plurality of address segments. The operations include determining an error correction code for the at least one address segment that includes one or more address check bits. The operations include generating a physical layout of memory components based on the memory scrambling information. The memory components include at least one of the plurality of address bus bits, and the one or more address check bits.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: June 1, 2021
    Assignee: Synopsys, Inc.
    Inventors: Hayk Grigoryan, Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Patent number: 10789398
    Abstract: A method for determining redundancy usage rate from a group of memory parameters and a memory yield of a System on a Chip (SoC), using the probabilistic redundancy usage rate and using that rate to calculate an optimal RSMA size. An SoC is then fabricated with the optimal RSMA size.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: September 29, 2020
    Assignee: Synopsys, Inc.
    Inventors: Suren Martirosyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Publication number: 20190035484
    Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.
    Type: Application
    Filed: September 28, 2018
    Publication date: January 31, 2019
    Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Patent number: 10192635
    Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 29, 2019
    Assignee: Synopsys, Inc.
    Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Patent number: 10115477
    Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: October 30, 2018
    Assignee: Synopsys, Inc.
    Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Publication number: 20180129769
    Abstract: A method for determining redundancy usage rate from a group of memory parameters and a memory yield of a System on a Chip (SoC), using the probabilistic redundancy usage rate and using that rate to calculate an optimal RSMA size. An SoC is then fabricated with the optimal RSMA size.
    Type: Application
    Filed: August 23, 2017
    Publication date: May 10, 2018
    Inventors: Suren Martirosyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Publication number: 20180130546
    Abstract: A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.
    Type: Application
    Filed: September 28, 2017
    Publication date: May 10, 2018
    Inventors: Grigor Tshagharyan, Gurgen Harutyunyan, Samvel Shoukourian, Yervant Zorian
  • Patent number: 9831000
    Abstract: An integrated circuit includes a memory and a memory test circuit, which when invoked to test the memory, is configured to generate one or more March tests applied to the memory. The memory test circuit is further configured to construct a table including a first index, a second index, and a first March test of the one or more March tests. The first index is associated with one or more families each characterized by a different length of the one or more March tests. The second index is associated with one or more mechanisms each characterized by a different property of the one or more March tests. The memory test circuit is further configured to generate a second March test from the first March test.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: November 28, 2017
    Assignee: SYNOPSYS, INC.
    Inventors: Aram Hakhumyan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
  • Patent number: 9541591
    Abstract: A fully-digital probabilistic measurement methodology in which a periodic signal generated on an IC device is sampled multiple times during a test period, with the asserted/de-asserted state of the periodic signal determined during each sampling event. A statistically significant number of sampling events are executed according to a reference signal frequency that is uncorrelated to the IC's system clock, whereby each successive sampling event involves detecting an essentially random associated phase of the periodic signal such that the probability of detecting an asserted state during any given sampling event is proportional to the duty cycle of the periodic signal. A first count value records the number of sampling events in which the periodic signal is asserted, and a second count value records the total number of sampling events performed, whereby a ratio of these two count values provides a statistical measurement of the periodic signal's duty cycle.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: January 10, 2017
    Assignee: Synopsys, Inc.
    Inventors: Karen Darbinyan, Yervant Zorian, Arun Kumar, Mher Mkhoyan
  • Patent number: 9514258
    Abstract: A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy between the physical bit patterns and the logical bit patterns. The strap distribution information and the address scrambling information are combined into the memory structural model used for designing an efficient test and repair engine.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: December 6, 2016
    Assignee: Synopsys, Inc.
    Inventors: Karen Amirkhanyan, Karen Darbinyan, Arman Davtyan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian
  • Patent number: 9336342
    Abstract: A memory hard macro designed to support multiple design for test (DFT) techniques having signal paths associated with the DFT techniques and the functional operation of the memory instance that share logic devices or components. The memory hard macro includes a functional input port and a functional output port, forming a functional memory data path, which includes input latches from the memory instance. The memory hard macro also includes a scan input port and a scan output port, forming a scan data path, which includes input latches from the array of data buffer circuits and output latches from the array of sense amplifiers. The memory hard macro further includes a BIST input port and a BIST output port, forming a BIST data path, which includes at least one input latch from the array of data buffer circuits and at least one output latch from the array of sense amplifiers.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: May 10, 2016
    Assignee: Synopsys, Inc.
    Inventors: Yervant Zorian, Karen Darbinyan, Gevorg Torjyan
  • Publication number: 20160041212
    Abstract: A fully-digital probabilistic measurement methodology in which a periodic signal generated on an IC device is sampled multiple times during a test period, with the asserted/de-asserted state of the periodic signal determined during each sampling event. A statistically significant number of sampling events are executed according to a reference signal frequency that is uncorrelated to the IC's system clock, whereby each successive sampling event involves detecting an essentially random associated phase of the periodic signal such that the probability of detecting an asserted state during any given sampling event is proportional to the duty cycle of the periodic signal. A first count value records the number of sampling events in which the periodic signal is asserted, and a second count value records the total number of sampling events performed, whereby a ratio of these two count values provides a statistical measurement of the periodic signal's duty cycle.
    Type: Application
    Filed: August 10, 2015
    Publication date: February 11, 2016
    Inventors: Karen Darbinyan, Yervant Zorian, Arun Kumar, Mher Mkhoyan
  • Patent number: 9053050
    Abstract: A desirable number of segments for a multi-segment single error correcting (SEC) coding scheme is determined based on scrambling information for a memory. The desirable number of segments can be the minimum number of segments required to satisfy a masked write segmentation requirement and a multi-bit upset size requirement. In one aspect, the memory scrambling information can specify the different scrambling techniques employed by the memory (e.g., Input-Output (IO) cell scrambling, column scrambling, column twisting, strap distribution, etc.). Based on the scrambling information, a mapping between the logical structure and physical layout for the memory can be derived. The mapping can be used to determine the least number of segments needed to satisfy the masked write requirement and the multi-bit upset size requirement.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: June 9, 2015
    Assignee: Synopsys, Inc.
    Inventors: Hayk Grigoryan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian