Abstract: Various methods and apparatuses are described in which a repair data container may store a concatenated repair signature for multiple memories having one or more redundant components associated with each memory. A processor contains redundancy allocation logic to execute one or more repair algorithms to generate a repair signature for each memory. The repair data container may store actual repair signatures for each memory having one or more defective memory cells detected during fault testing and dummy repair signatures for each memory with no defective memory cells. The processor may contain logic configured to compress an amount of bits making up the concatenated repair signature, to decompress the amount of bits making up the concatenated repair signature, and to compose the concatenated repair signature for all of the memories sharing the repair data container. The repair data container may have an amount of fuses to store the actual repair signatures for an adjustable subset of the multiple memories.

Abstract: A method and system for repairing a memory. A test and repair wrapper is operable to be integrated with input/output (I/O) circuitry of a memory instance to form a wrapper I/O (WIO) block that is operable to receive test and repair information from a built-in self-test and repair (BISTR) processor. Logic circuitry associated with the WIO block is operable generate a current error signal that is used locally by the BISTR processor for providing a repair enable control signal in order to repair a faulty memory portion using a redundant memory portion without having to access a post-processing environment for repair signature generation.

Abstract: Architecture, system and method for providing compression of repair data in an IC design having a plurality of memory instances. In one embodiment, the repair data storage method includes determining repair data for each of the memory instances and compressing the repair data into a compressed format that is stored in a shared nonvolatile storage common to the memory instances.

Abstract: Methods and apparatuses in which two or more memories share a processor for Built In Self Test algorithms and features are described. The processor initiates a Built In Self Test for the memories. Each memory has an intelligence wrapper bounding that memory. Each intelligence wrapper contains control logic to decode a command from the processor. Each intelligence wrapper contains logic to execute a set of test vectors on a bounded memory. The processor sends a command based self-test to each intelligence wrapper at a first clock speed and the control logic executes the operations associated with that command at a second clock speed asynchronous with the first speed. The processor loads the command containing representations of a march element and data to one or more of the intelligence wrappers via a serial bus.

Abstract: In general, various methods, apparatuses, and systems that generate an augmented repair signature to repair all of the defects detected in a first test of a memory as well as in a second test of the memory.

Abstract: Integrated circuit test circuits may include at least an instruction processor and input-output subsystems. Input-output subsystems are segmented together into input-output subsystem segments. Each input-output subsystem includes an analog wrapper circuit (IW-A) operable to connect an input-output port to analog buses and further operable to isolate the input-output port from the buses, an integrated wrapper for delay test circuit (WI-D) operable to control a delay test sequence, and a soft wrapper circuit operable to control the IW-A and the IW-D, the soft wrapper circuit being directed by the instruction processor.

Abstract: In general, various methods, apparatuses, and systems are described in which logic executes, in series, a plurality of repair algorithms to generate a repair signature for a memory. The memory has a full set of redundant components associated with the memory. At least one or more of the repair algorithms employ a subset of redundant components that contains less than all of the redundant components in the full set when attempting to generate the repair signature.

Abstract: In general, various methods, apparatuses, and systems in which a processor that contains self test and repair instructions to be executed on a memory is coupled to a first external pin. Assertion of a signal on the first external pin activates execution of the self-test and repair instructions on the memory.

Abstract: In general, a method, apparatus, and system determine the allocation of the one or more redundant components while fault testing the memory. In an embodiment of an apparatus, one or more memories and one or more processors are located on a single chip. Each memory has one or more redundant components associated with that memory. The one or more redundant components include at least one redundant column. The one or more processors contain redundancy allocation logic having an algorithm. The algorithm determines the allocation of the one or more redundant components to repair one or more defects detected in the one or more memories while fault testing the memory.

Abstract: A reconfiguration memory device is provided associated with a main memory array. The reconfiguration memory device generates a spare address in real time corresponding to a faulty address. The reconfiguration memory device is coupled to an address line, so that when address information is received for the main memory array, the address information is also received by the reconfiguration memory device. The reconfiguration memory device is adapted to send an output signal that results in the address in the spare memory address array being addressed, if the received address information corresponds to a stored faulty address. The output signal includes a spare control signal that directs components to look to the output of the spare memory.

Abstract: A reconfiguration memory device is provided associated with a main memory array. The reconfiguration memory device generates a spare address in real time corresponding to a faulty address. The reconfiguration memory device is coupled to an address line, so that when address information is received for the main memory array, the address information is also received by the reconfiguration memory device. The reconfiguration memory device is adapted to send an output signal that results in the address in the spare memory address array being addressed, if the received address information corresponds to a stored faulty address. The output signal includes a spare control signal that directs components to look to the output of the spare memory.

Abstract: DRAM memory unit is tested for a series of cell faults such as: the stuck-at fault (SAF), the stuck-open fault (SOF), the transition fault (TF), the multiple address fault (MAF) as well as storage capacitor leakage, subthreshold leakage or junction leakage. Predetermined data pattern is written throughout the DRAM memory, locations in one region of the memory are “frozen” while a disturbance is created in a second region during an interval sufficient for a defective cell in the first region to lose its charge, following which the locations of the first region are sequentially read to verify if any cell has lost its data.

Abstract: A method is provided for determining the location of faulty components in a computer memory array on a chip and for providing a software repair procedure. According to the method, the location of faulty components in a computer memory array is determined by successively reading and writing to locations in the array according to an algorithm. If a faulty component is detected, it is determined whether a spare component in a spare memory array on the chip is available. If a spare component is available, a spare component is designated to correspond to the faulty component. A look up table on the same chip stores information representing the location of the faulty component associated with information representing the location of the corresponding spare component.

Abstract: This invention relates to a token passing network, called a Universal BIST Scheduler (UBS), and a method for scheduling BISTed memory elements based on: executing BIST in multiple stages in order to optimize the efficiency of continuous processing and to apply a single waiting period to multiple SBRIC_RSs where, for example, BIST includes retention testing; dividing resource controllers or SBRIC_RSs corresponding to one or more RSB elements into a matrix such that each SBRIC_RS executes the BIST of its memory elements concurrently and/or successively depending on the SBRIC_RS's position in the matrix; and passing a token to initiate processing of a set of SBRIC_RSs in the matrix through a level signal rather than a pulse signal in order to ensure that the signal is not lost.

Abstract: A method and apparatus are described for detecting an optimized set of predetermined faults in a memory device which ensure an acceptable quality level. The method and apparatus comprise a BIST March algorithm optimized to accelerate the testing time by reducing the number of read/write operations necessary to detect a set of predetermined faults.

Abstract: This invention relates to a token passing network, called a Universal BIST Scheduler (UBS), and a method for scheduling BISTed memory elements based on: executing BIST in multiple stages in order to optimize the efficiency of continuous processing and to apply a single waiting period to multiple SBRIC.sub.-- RSs where, for example, BIST includes retention testing; dividing resource controllers or SBRIC.sub.-- RSs corresponding to one or more RSB elements into a matrix such that each SBRIC.sub.-- RS executes the BIST of its memory elements concurrently and/or successively depending on the SBRIC.sub.-- RS's position in the matrix; and passing a token to initiate processing of a set of SBRIC.sub.-- RSs in the matrix through a level signal rather than a pulse signal in order to ensure that the signal is not lost.

Abstract: A dual-port RAM-type ring-address FIFO including a data input register with a set of transparent latches is tested by causing the FIFO to execute a test method comprised of a set of interwoven steps. Upon execution, the steps of the method cause the FIFO to manifest all possible memory, address and functional faults. This test method manifests faults by causing the FIFO to alter the state of various flags it normally sets and by altering the logic state of the data normally produced by the FIFO.

Abstract: A Built-In Self Test (BIST) method and apparatus for Booth multipliers, wherein a fixed-size (8-bit) binary counter is used along with accumulator-based output data compaction. The fault model adopted enables a BIST algorithm which is independent of specific gate level implementations of the multiplier cells. The generated 256 test vectors guarantee more than 99% single stuck-at fault coverage. A new accumulator-based compaction scheme is introduced to provide less aliasing and thus higher compaction quality than existing accumulator-based approaches. No design for testability modifications to the multiplier are required and method is totally applied on the periphery of the multiplier structure therefor causing no internal performance degradation. The BIST scheme of the present invention is generic and can be applied to any Booth multiplier derived by any module generator.

Abstract: Control of the self-testing of a plurality of elements (12.sub.1 -12.sub.m), each having a Built-In, Self-Test (BIST) capability, and arranged in one or more groups (14.sub.1 -14.sub.n), is carried out by a network (16) of one or more standard BIST resource interface controllers (SBRICs 18.sub.1 -18.sub.n). Each SBRIC in the network controls the self-testing of the elements in a separate one of the groups in sequence by broadcasting a test command to the elements in parallel which, in response, generate test signatures stored by the SBRIC. The SBRICs in the network are coupled in series in daisy chain fashion to enable the test signatures stored by the SBRICs to be concatenated for easy retrieval by shifting out the test signatures therefrom, using a technique such as boundary scan.

Abstract: A dual-port, RAM-type ring-address FIFO (100) is tested by causing the FIFO to execute a composite test method comprised of set of interwoven steps (( 1 )-(31 ) or (1')-(25')). Upon execution, the steps of the composite method cause the FIFO (100) to manifest all possible memory, address and functional faults. The test method manifests faults by causing the FIFO (100) to alter the state of the various flags it normally sets and by altering the logic state of the data normally produced by the FIFO.