Abstract: A connecting device used for electrically connecting a power source with a power consuming module is provided. The connecting device includes a female connecting base and a male connecting base. The female connecting base has two opposite surfaces, a rim disposed on one of the surfaces and two terminals exposed on the surfaces. The terminals are connected to the live wire and neutral wire of the power source separately. The male connecting base includes a clamp, two conductive strips, and a ground strip. The rim is clamped, and the male connecting base is fastened to the female connecting base by the clamp. The terminals are connected to the conductive strips, while the end surface of each conductive strip protrudes from the surface of the male connecting base. The ground strip includes a ground surface which protrudes from the end surfaces of the conductive strips.

Abstract: Certain aspects of the present disclosure provide techniques for securely accessing a wallet maintained by a centralized platform on a blockchain. An example method generally includes receiving a request to access one or more wallets on a blockchain. Generally, the request includes an authorization code associated with a controlling party associated with the one or more wallets and user credentials associated with the controlling party. A first portion of a private key is decrypted based on the authorization code and a salt associated with the user credentials associated with the controlling party, and a second portion of the private key is decrypted based on credentials associated with an application through which the wallet is accessed. Access to the one or more wallets is granted based on the decrypted first portion and the decrypted second portion of the private key.

Abstract: Certain aspects of the present disclosure provide techniques for securely accessing a wallet on a blockchain. An example method generally includes receiving a request to access a wallet on a blockchain. The request generally includes an authorization code associated with the wallet and user credentials associated with an owner of the wallet. A first portion of a private key is decrypted based on the authorization code and a salt associated with the user credentials, and a second portion of the private key is decrypted based on credentials associated with an application through which the wallet is accessed. Access to the wallet is granted based on the decrypted first portion and the decrypted second portion of the private key.

Abstract: Certain aspects of the present disclosure provide techniques for securely accessing a wallet maintained by a centralized platform on a blockchain. An example method generally includes receiving a request to access one or more wallets on a blockchain. Generally, the request includes an authorization code associated with a controlling party associated with the one or more wallets and user credentials associated with the controlling party. A first portion of a private key is decrypted based on the authorization code and a salt associated with the user credentials associated with the controlling party, and a second portion of the private key is decrypted based on credentials associated with an application through which the wallet is accessed. Access to the one or more wallets is granted based on the decrypted first portion and the decrypted second portion of the private key.

Abstract: Provided herein are functional moieties, functionalized compounds and macromolecules, their preparation, and uses thereof.

Abstract: A semiconductor device includes a conductive pad over an interconnect structure, wherein the conductive pad is electrically connected to an active device. The semiconductor device further includes a dielectric layer over the conductive pad, wherein the dielectric layer has a first conformity. The semiconductor device further includes a passivation layer over the dielectric layer, wherein the passivation layer has a second conformity different from the first conformity.

Abstract: A semiconductor die includes a semiconductor substrate, a dielectric layer over the semiconductor substrate, a metal structure in the dielectric layer, a first metal pad over the metal structure, a first oxide-based passivation layer over the first metal pad, a second oxide-based passivation layer over the first oxide-based passivation layer, and a bump electrically connected to the first metal pad. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.

Abstract: A semiconductor device includes a conductive pad over an interconnect structure, wherein the conductive pad is electrically connected to an active device. The semiconductor device further includes a dielectric layer over the conductive pad, wherein the dielectric layer has a first conformity. The semiconductor device further includes a passivation layer over the dielectric layer, wherein the passivation layer has a second conformity different from the first conformity.

Abstract: An integrated circuit (IC) device includes a redistribution line over a substrate, wherein a first angle between a topmost surface of the redistribution line and a sidewall of the redistribution line is within a first angle range, a second angle between a bottommost surface of the redistribution line and the sidewall of the redistribution line is within a second angle range, and the second angle range is different from the first angle range. The IC device further includes a passivation layer over the redistribution line, wherein a bottommost surface of the passivation layer is below the bottommost surface of the redistribution line.

Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

Abstract: The present invention relates to a multilayer sheet comprising at least two layers (A) and (B) in adherent contact with each other, wherein layer (A) is a foamed sheet comprising a high melt strength polypropylene composition and layer (B) is a coated non-foamed layer, which comprises a polypropylene composition, a process for producing said multilayer sheet, an article comprising said multilayer sheet and the use of said multilayer sheet for the production of an article with improved water vapor transmission and oxygen transmission properties.

Abstract: An integrated circuit (IC) device includes a redistribution line over a substrate, wherein an entire sidewall of the redistribution line is curved. The IC device further includes a passivation layer over the redistribution line, wherein a distance from a bottommost surface of the passivation layer to the substrate is less than a distance from a bottommost surface of the redistribution line to the substrate. The IC device further includes a polymer layer over the passivation layer.

Abstract: The present invention relates to a foamed sheet consisting of a polypropylene composition comprising at least 85 wt. %, e.g. from 85 to 99.5 wt.-%, of a high melt strength polypropylene (HMS-PP) and 0.5 to 15 wt. % of a nucleating agent (NA), wherein the foamed sheet has a thickness of below 0.5 mm or a thickness of 2.0 mm or more. The present invention further relates to a foamed material consisting of a polypropylene composition as well as the use of a polypropylene composition comprising at least 85 wt. %, e.g. from 85 to 99.5 wt.-%, of a high melt strength polypropylene (HMS-PP) and 0.5 to 15 wt. % of a nucleating agent (NA) for producing foamed material.

Abstract: The present invention relates to a polypropylene composition comprising —10 to 50 wt. % of recycled polypropylene (R-PP) and/or linear polypropylene (L-PP); —40 to 89.95 wt. % of a high melt strength polypropylene (HMS-PP) having an F30 melt strength of more than 25.0 cN and a v30 melt extensibility of more than 205 mm/s, wherein the F30 melt strength and the v30 melt extensibility are determined according to ISO 16790:2005; and —0.05 to 10 wt. % of a nucleating agent (NA); a foamed sheet formed from the polypropylene composition; an article comprising the foamed sheet and a process comprising the step of forming the polypropylene composition. Furthermore, the invention is further directed to the usage of the polypropylene composition for the formation of foamed sheets.

Abstract: A semiconductor die includes a semiconductor substrate, a dielectric layer over the semiconductor substrate, a metal structure in the dielectric layer, a first metal pad over the metal structure, a first oxide-based passivation layer over the first metal pad, a second oxide-based passivation layer over the first oxide-based passivation layer, and a bump electrically connected to the first metal pad. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.

Abstract: A method is provided. A bottom passivation layer is formed on a dielectric layer over a semiconductor substrate. Then, a first opening is formed in the bottom passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. Afterwards, a first oxide-based passivation layer is formed over the metal pad. Then, a second oxide-based passivation layer is formed over the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.

Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

Abstract: An integrated circuit (IC) device includes a redistribution line over a substrate, wherein an entire sidewall of the redistribution line is curved. The IC device further includes a passivation layer over the redistribution line, wherein a distance from a bottommost surface of the passivation layer to the substrate is less than a distance from a bottommost surface of the redistribution line to the substrate. The IC device further includes a polymer layer over the passivation layer.

Abstract: An integrated circuit (IC) device includes a first passivation layer over a substrate. The IC device further includes a redistribution line over the first passivation layer, wherein the redistribution line has a barrel-shaped profile. The IC device further includes a second passivation layer over the redistribution line. The IC device further includes a polymer layer over the second passivation layer.

Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.