Patents by Inventor Yi-An Lin

Yi-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210265292
    Abstract: A semiconductor device includes a conductive pad over an interconnect structure, wherein the conductive pad is electrically connected to an active device. The semiconductor device further includes a dielectric layer over the conductive pad, wherein the dielectric layer has a first conformity. The semiconductor device further includes a passivation layer over the dielectric layer, wherein the passivation layer has a second conformity different from the first conformity.
    Type: Application
    Filed: May 13, 2021
    Publication date: August 26, 2021
    Inventors: Yu-Lung SHIH, Chao-Keng LI, Alan KUO, C. C. CHANG, Yi-An LIN
  • Patent number: 11018100
    Abstract: A semiconductor device includes a conductive pad over an interconnect structure, wherein the conductive pad is electrically connected to an active device. The semiconductor device includes a dielectric layer over the conductive pad, wherein the dielectric layer comprises silicon oxide. The semiconductor device includes a first passivation layer directly over the dielectric layer, wherein the first passivation layer comprises silicon oxide. The semiconductor device includes a second passivation layer directly over the first passivation layer, wherein the second passivation layer comprises silicon nitride.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: May 25, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lung Shih, Chao-Keng Li, Alan Kuo, C. C. Chang, Yi-An Lin
  • Publication number: 20200381326
    Abstract: A method is provided. A bottom passivation layer is formed on a dielectric layer over a semiconductor substrate. Then, a first opening is formed in the bottom passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. Afterwards, a first oxide-based passivation layer is formed over the metal pad. Then, a second oxide-based passivation layer is formed over the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.
    Type: Application
    Filed: August 19, 2020
    Publication date: December 3, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Ting WANG, Yi-An LIN, Ching-Chuan CHANG, Po-Chang KUO
  • Patent number: 10797156
    Abstract: A method includes depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature. The method includes performing a first chemical mechanical planarization (CMP) to expose the gate. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Neng-Kuo Chen, Clement Hsingjen Wann, Yi-An Lin, Chun-Wei Chang, Sey-Ping Sun
  • Patent number: 10755995
    Abstract: A method is provided. A bottom passivation layer is formed on a dielectric layer over a semiconductor substrate. Then, a first opening is formed in the bottom passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. Afterwards, a first oxide-based passivation layer is formed over the metal pad. Then, a second oxide-based passivation layer is formed over the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Ting Wang, Yi-An Lin, Ching-Chuan Chang, Po-Chang Kuo
  • Publication number: 20200258784
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Application
    Filed: May 1, 2020
    Publication date: August 13, 2020
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 10651091
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Publication number: 20200127118
    Abstract: A method includes depositing a contact etch stop layer (CESL) over a gate, a source/drain (S/D) region and an isolation feature. The method includes performing a first chemical mechanical planarization (CMP) to expose the gate. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the gate.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 23, 2020
    Inventors: Neng-Kuo CHEN, Clement Hsingjen WANN, Yi-An LIN, Chun-Wei CHANG, Sey-Ping SUN
  • Publication number: 20200051934
    Abstract: An integrated circuit (IC) device includes a first passivation layer over a substrate. The IC device further includes a redistribution line over the first passivation layer, wherein the redistribution line has a barrel-shaped profile. The IC device further includes a second passivation layer over the redistribution line. The IC device further includes a polymer layer over the second passivation layer.
    Type: Application
    Filed: October 21, 2019
    Publication date: February 13, 2020
    Inventors: Yi-An LIN, Alan KUO, C. C. CHANG, Yu-Lung SHIH
  • Publication number: 20200006182
    Abstract: A method is provided. A bottom passivation layer is formed on a dielectric layer over a semiconductor substrate. Then, a first opening is formed in the bottom passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. Afterwards, a first oxide-based passivation layer is formed over the metal pad. Then, a second oxide-based passivation layer is formed over the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.
    Type: Application
    Filed: May 2, 2019
    Publication date: January 2, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Ting WANG, Yi-An LIN, Ching-Chuan CHANG, Po-Chang KUO
  • Patent number: 10516031
    Abstract: A method of fabricating a semiconductor device includes depositing a contact etch stop layer (CESL) over a dummy gate electrode, a source/drain (S/D) region and an isolation feature. The method further includes performing a first CMP to expose the dummy gate electrode. The method further includes removing an upper portion of the CESL. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the dummy gate electrode.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Neng-Kuo Chen, Clement Hsingjen Wann, Yi-An Lin, Chun-Wei Chang, Sey-Ping Sun
  • Patent number: 10453811
    Abstract: A method of manufacturing a semiconductor structure. The method includes depositing a conductive material over a substrate, and removing a portion of the conductive material to form a conductive structure having a barrel shape. A width of a body portion of the conductive structure is greater than a width of an upper portion and a width of a bottom portion of the conductive structure.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: October 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-An Lin, Alan Kuo, C. C. Chang, Yu-Lung Shih
  • Publication number: 20190273056
    Abstract: A semiconductor device includes a conductive pad over an interconnect structure, wherein the conductive pad is electrically connected to an active device. The semiconductor device includes a dielectric layer over the conductive pad, wherein the dielectric layer comprises silicon oxide. The semiconductor device includes a first passivation layer directly over the dielectric layer, wherein the first passivation layer comprises silicon oxide. The semiconductor device includes a second passivation layer directly over the first passivation layer, wherein the second passivation layer comprises silicon nitride.
    Type: Application
    Filed: May 13, 2019
    Publication date: September 5, 2019
    Inventors: Yu-Lung SHIH, Chao-Keng LI, Alan KUO, C. C. CHANG, Yi-An LIN
  • Patent number: 10391608
    Abstract: A wafer polishing apparatus is described herein. The wafer polishing apparatus includes a polish module configured to apply air pressure to a first surface of a wafer while performing a polishing process on a second surface of the wafer. In some implementations, the polish module is further configured to perform a cleaning process and/or a drying process on the second surface of the wafer, such that the same wafer polishing apparatus is configured to perform the polishing process, the cleaning process, and/or the drying process. In some implementations, the polishing module is further configured to air seal edges of the wafer during the polishing process, the cleaning process, and/or the drying process.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: August 27, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hung Chen, Chia-Jung Hsu, Yi-An Lin
  • Publication number: 20190252261
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 10290596
    Abstract: A method of making a semiconductor device includes depositing a dielectric layer over a conductive pad using a first deposition process. The method further includes depositing a first passivation layer directly over the dielectric layer using a high density plasma chemical vapor deposition (HDPCVD). The first deposition process is different from HDPCVD. A thickness of the dielectric layer is sufficient to prevent charges generated by depositing the first passivation layer from reaching the conductive pad.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lung Shih, Chao-Keng Li, Alan Kuo, C. C. Chang, Yi-An Lin
  • Patent number: 10269649
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Publication number: 20180219077
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Application
    Filed: March 28, 2018
    Publication date: August 2, 2018
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Publication number: 20180201752
    Abstract: Cups based on a multi-layered sheet comprising at least one foamed layer based on high melt strength polypropylene and a nucleating agent.
    Type: Application
    Filed: July 29, 2016
    Publication date: July 19, 2018
    Inventor: Yi An Lin
  • Publication number: 20180166406
    Abstract: A method of making a semiconductor device includes depositing a dielectric layer over a conductive pad using a first deposition process. The method further includes depositing a first passivation layer directly over the dielectric layer using a high density plasma chemical vapor deposition (HDPCVD). The first deposition process is different from HDPCVD. A thickness of the dielectric layer is sufficient to prevent charges generated by depositing the first passivation layer from reaching the conductive pad.
    Type: Application
    Filed: June 8, 2017
    Publication date: June 14, 2018
    Inventors: Yu-Lung SHIH, Chao-Keng LI, Alan KUO, C. C. CHANG, Yi-An LIN