Patents by Inventor Yi-An Lin
Yi-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180151520Abstract: A method of manufacturing a semiconductor structure. The method includes depositing a conductive material over a substrate, and removing a portion of the conductive material to form a conductive structure having a barrel shape. A width of a body portion of the conductive structure is greater than a width of an upper portion and a width of a bottom portion of the conductive structure.Type: ApplicationFiled: May 1, 2017Publication date: May 31, 2018Inventors: Yi-An LIN, Alan KUO, C. C. CHANG, Yu-Lung SHIH
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Publication number: 20180138052Abstract: A wafer polishing apparatus is described herein. The wafer polishing apparatus includes a polish module configured to apply air pressure to a first surface of a wafer while performing a polishing process on a second surface of the wafer. In some implementations, the polish module is further configured to perform a cleaning process and/or a drying process on the second surface of the wafer, such that the same wafer polishing apparatus is configured to perform the polishing process, the cleaning process, and/or the drying process. In some implementations, the polishing module is further configured to air seal edges of the wafer during the polishing process, the cleaning process, and/or the drying process.Type: ApplicationFiled: December 27, 2017Publication date: May 17, 2018Inventors: Chih-Hung Chen, Chia-Jung Hsu, Yi-An Lin
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Patent number: 9941367Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: GrantFiled: August 2, 2016Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20180069094Abstract: A method of fabricating a semiconductor device includes depositing a contact etch stop layer (CESL) over a dummy gate electrode, a source/drain (S/D) region and an isolation feature. The method further includes performing a first CMP to expose the dummy gate electrode. The method further includes removing an upper portion of the CESL. The method further includes performing a second CMP using a slurry different from the first CMP to expose the CESL over the S/D region, wherein, following the second CMP, an entire top surface of the CESL over the S/D region and over the isolation feature is substantially level with a top surface of the dummy gate electrode.Type: ApplicationFiled: October 31, 2017Publication date: March 8, 2018Inventors: Neng-Kuo CHEN, Clement Hsingjen WANN, Yi-An LIN, Chun-Wei CHANG, Sey-Ping SUN
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Patent number: 9865477Abstract: The present disclosure provides a semiconductor fabrication apparatus in accordance with one embodiment. The apparatus includes a wafer stage that is operable to secure and rotate a wafer; a polish head configured to polish a backside surface of the wafer; an air bearing module configured to apply an air pressure to a front surface of the wafer; and an edge sealing unit configured to seal edges of the wafer.Type: GrantFiled: February 24, 2016Date of Patent: January 9, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hung Chen, Chia-Jung Hsu, Yi-An Lin
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Patent number: 9812551Abstract: This description relates to a method of forming the gate electrode of a semiconductor device, the method including providing a substrate comprising a dummy gate electrode (DGE), a source/drain (S/D) region, a spacer on a dummy gate sidewall, and an isolation feature, depositing a contact etch stop layer (CESL) over the DGE, the S/D region and the spacer, depositing an interlayer dielectric (ILD) layer over the CESL, performing a first chemical mechanical polishing (CMP) to expose the CESL over the DGE, performing a second CMP to expose the DGE, removing an upper portion of the CESL and the spacer, and performing a third CMP to expose the CESL over the S/D region to produce a structure in which an entire top surface of the CESL over the S/D region and isolation feature is substantially co-planar with a top surface of the DGE.Type: GrantFiled: February 21, 2017Date of Patent: November 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Neng-Kuo Chen, Clement Hsingjen Wann, Yi-An Lin, Chun-Wei Chang, Sey-Ping Sun
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Publication number: 20170243733Abstract: The present disclosure provides a semiconductor fabrication apparatus in accordance with one embodiment. The apparatus includes a wafer stage that is operable to secure and rotate a wafer; a polish head configured to polish a backside surface of the wafer; an air bearing module configured to apply an air pressure to a front surface of the wafer; and an edge sealing unit configured to seal edges of the wafer.Type: ApplicationFiled: February 24, 2016Publication date: August 24, 2017Inventors: Chih-Hung Chen, Chia-Jung Hsu, Yi-An Lin
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Publication number: 20170162669Abstract: This description relates to a method of forming the gate electrode of a semiconductor device, the method including providing a substrate comprising a dummy gate electrode (DGE), a source/drain (S/D) region, a spacer on a dummy gate sidewall, and an isolation feature, depositing a contact etch stop layer (CESL) over the DGE, the S/D region and the spacer, depositing an interlayer dielectric (ILD) layer over the CESL, performing a first chemical mechanical polishing (CMP) to expose the CESL over the DGE, performing a second CMP to expose the DGE, removing an upper portion of the CESL and the spacer, and performing a third CMP to expose the CESL over the S/D region to produce a structure in which an entire top surface of the CESL over the S/D region and isolation feature is substantially co-planar with a top surface of the DGE.Type: ApplicationFiled: February 21, 2017Publication date: June 8, 2017Inventors: Neng-Kuo CHEN, Clement Hsingjen WANN, Yi-An LIN, Chun-Wei CHANG, Sey-Ping SUN
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Patent number: 9589803Abstract: This description relates to a gate electrode of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate electrode over the substrate including a first top surface and a sidewall; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and the S/D region; and a contact etch stop layer (CESL) adjacent to the spacer and further comprising a portion extending over the S/D region, wherein the portion has a second top surface substantially coplanar with the first top surface.Type: GrantFiled: August 10, 2012Date of Patent: March 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Neng-Kuo Chen, Clement Hsingjen Wann, Yi-An Lin, Chun-Wei Chang, Sey-Ping Sun
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Publication number: 20160343815Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.Type: ApplicationFiled: August 2, 2016Publication date: November 24, 2016Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 9443769Abstract: Fin structures are formed on a substrate. An isolation region is between the fin structures. The fin structures comprise epitaxial regions extending above the isolation region. Each of the epitaxial regions has a widest mid-region between an upper-surface and an under-surface. A dual-layer etch stop is formed over the fin structures and comprises a first sub-layer and a second sub-layer. The first sub-layer is along the upper- and under-surfaces and the isolation region. The second sub-layer is over the first sub-layer and along the upper-surfaces, and the second sub-layer merges together proximate the widest mid-regions of the epitaxial regions. Portions of the dual-layer etch stop are removed from the upper- and under-surfaces. A dielectric layer is formed on the upper- and under-surfaces. A metal layer is formed on the dielectric layer on the upper-surfaces. A barrier layer is formed on the metal layer and along the under-surfaces.Type: GrantFiled: April 21, 2014Date of Patent: September 13, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 9337103Abstract: A method includes forming a first gate above a semiconductor substrate, forming a hard mask on the first gate, and forming a contact etch stop layer (CESL) on the hard mask. No hard mask is removed between the step of forming the hard mask and the step of forming the CESL. The method further includes forming an interlayer dielectric (ILD) layer over the CESL, and performing one or more CMP processes to planarize the ILD layer, remove the CESL on the hard mask, and remove at least one portion of the hard mask.Type: GrantFiled: December 7, 2012Date of Patent: May 10, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-An Lin, Chun-Wei Chang, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 9263252Abstract: This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures.Type: GrantFiled: January 7, 2013Date of Patent: February 16, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Wei Chang, Yi-An Lin, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann, Yu-Lien Huang
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Publication number: 20150303118Abstract: Fin structures are formed on a substrate. An isolation region is between the fin structures. The fin structures comprise epitaxial regions extending above the isolation region. Each of the epitaxial regions has a widest mid-region between an upper-surface and an under-surface. A dual-layer etch stop is formed over the fin structures and comprises a first sub-layer and a second sub-layer. The first sub-layer is along the upper- and under-surfaces and the isolation region. The second sub-layer is over the first sub-layer and along the upper-surfaces, and the second sub-layer merges together proximate the widest mid-regions of the epitaxial regions. Portions of the dual-layer etch stop are removed from the upper- and under-surfaces. A dielectric layer is formed on the upper- and under-surfaces. A metal layer is formed on the dielectric layer on the upper-surfaces. A barrier layer is formed on the metal layer and along the under-surfaces.Type: ApplicationFiled: April 21, 2014Publication date: October 22, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 9072127Abstract: A lighting system, which is composed of a redundant power supply and at least one luminaire with a lamp control module contained therein. The lamp control module includes at least one light source and a light control module. The light control module includes a current control unit, at least one switch unit, and a processing unit. The current control unit is to control the DC current. The switch unit is electrically connected to the light source and enables the DC current source to selectively control DC current to at least one light source. The processing unit is used to adjust value of DC current. The luminaire includes the lamp control module, housing and power lines. The redundant power supply contains at least one AC-to-DC converter module, and the redundant power supply provides constant DC power to at least one light control module of the luminaire.Type: GrantFiled: April 12, 2013Date of Patent: June 30, 2015Assignee: RADIANT OPTO-ELECTRONICS CORPORATIONInventors: Cheng-Lin Lu, Yi-An Lin, Kun-Feng Chen, Ko-Yu Hsiao
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Patent number: 8940597Abstract: A method of producing a metal gate structure. The method includes forming a gate structure above a semiconductor substrate and performing one or more chemical metal planarization (CMP) processes to planarize the formed gate structure using a CMP tool. An in situ gate etching process is performed in a CMP cleaner of the CMP tool to form a gate recess. A contact etch stop layer (CESL) can then be deposited in the formed gate recess and one or more CMP processes performed to planarize the CESL.Type: GrantFiled: March 11, 2013Date of Patent: January 27, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Jung Hsu, Gin-Chen Huang, Yi-An Lin, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann
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Patent number: 8853052Abstract: A method for fabricating a semiconductor device is disclosed. An exemplary method includes a providing substrate. A dielectric layer is formed over the semiconductor substrate and a stop layer is formed over the dielectric layer. The stop layer and the dielectric layer comprise a different material. The method further includes forming a patterned hard mask layer over the stop layer and etching the semiconductor substrate through the patterned hard mask layer to form a plurality of trenches. The method also includes depositing an isolation material on the semiconductor substrate and substantially filling the plurality of trenches. Thereafter, performing a CMP process on the semiconductor substrate, wherein the CMP process stops on the stop layer.Type: GrantFiled: August 5, 2011Date of Patent: October 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Gin-Chen Huang, Yi-An Lin, Ching-Hong Jiang, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20140256124Abstract: A method of producing a metal gate structure. The method includes forming a gate structure above a semiconductor substrate and performing one or more chemical metal planarization (CMP) processes to planarize the formed gate structure using a CMP tool. An in situ gate etching process is performed in a CMP cleaner of the CMP tool to form a gate recess. A contact etch stop layer (CESL) can then be deposited in the formed gate recess and one or more CMP processes performed to planarize the CESL.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Jung Hsu, Gin-Chen Huang, Yi-An Lin, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann
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Publication number: 20140258267Abstract: Methods and systems directed to aggregating social content from social networking sites, and making the social content available for searching is disclosed. Social content, corresponding to multiple computer users, is obtained from a plurality of social networking sites. The social content is stored in a content store, making it available for searching. In response to receiving a search query (directed to social content), a set of search results is identified, the search results including at least one item of social content obtained from a social networking site. The social content in the search results is filtered according to privacy constraints. A presentation of the filtered search results is generated and provided to the requesting computer user.Type: ApplicationFiled: March 8, 2013Publication date: September 11, 2014Applicant: MICROSOFT CORPORATIONInventors: Yi-An Lin, Timothy Andrew Harrington, Guenther Schmuelling, Zhi Liang Lu
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Publication number: 20140191333Abstract: This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures.Type: ApplicationFiled: January 7, 2013Publication date: July 10, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Wei CHANG, Yi-An LIN, Neng-Kuo CHEN, Sey-Ping SUN, Clement Hsingjen WANN, Yu-Lien HUANG