Abstract: Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16.

Abstract: Provided is a semiconductor device including a substrate. A gate formed on the substrate. The gate includes a sidewall. A spacer formed on the substrate and adjacent the sidewall of the gate. The spacer has a substantially triangular geometry. A contact etch stop layer (CESL) is formed on the first gate and the first spacer. The thickness of the CESL to the width of the first spacer is between approximately 0.625 and 16.

Abstract: Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes the conductive liner contacting the portion of the surface of the first conductive layer. A trench structure is formed on the via structure in the dielectric without the conductive liner layer in the trench.

Abstract: A box-spring assembly includes two frames, a resilient member, a plurality of lateral springs, and a plurality of clips. The frames are spaced apart from each other, and each of the frames has a looped lateral frame rod. The resilient member includes an array of spring coil units disposed between the frames, and a plurality of connecting elements connecting the spring coil units to each other. Each of the lateral springs is connected between the looped lateral frame rods so as to reinforce the looped lateral frame rods. The clips connect the spring coil units and the lateral springs to the looped lateral frame rods.

Abstract: Via hole and trench structures and fabrication methods are disclosed. The structure includes a conductive layer in a dielectric layer, and a via structure in the dielectric layer contacting a portion of a surface of the conductive layer. The via structure includes the conductive liner contacting the portion of the surface of the first conductive layer. A trench structure is formed on the via structure in the dielectric without the conductive liner layer in the trench.

Abstract: A method for forming a metal filled semiconductor feature with improved structural stability including a semiconductor wafer having an anisotropically etched opening formed through a plurality of dielectric insulating layers revealing a first etching resistant layer overlying a conductive area; a plurality of dielectric insulating layers sequentially stacked to have alternating etching rates to a preferential etching process; subjecting the anisotropically etched opening to the preferential etching process whereby the sidewalls of the anisotropically etched opening are preferentially etched to produce etched dielectric insulating layers to form roughened sidewall surfaces; anisotropically etching through the etching resistant layer to reveal the conductive area; and, filling the anisotropically etched opening with a metal to form a metal filled semiconductor feature.

Abstract: Via hole and trench structures and fabrication methods are disclosed. The structure comprises a conductive layer in a dielectric layer, and a via hole in the dielectric layer for exposing a portion of a surface of the conductive layer. A conductive liner covers the exposed surface of the first conductive layer. A trench is formed on the via hole in the dielectric without the conductive liner layer in the trench. Dual damascene structures and fabrications methods are also disclosed. Following the fabrication methods of the via hole and trench structures, a conductive layer is further formed in the via hole and trench structures.

Abstract: A method for fabricating dual damascene structures having improved IC performance and reduced RC delay characteristics is provided. In one embodiment, a substrate with an etch stop layer formed thereon is provided. A dielectric layer is formed on the etch stop layer and an anti-reflective coating layer is formed on the dielectric layer. A first patterned photoresist layer having a via hole pattern is formed on the anti-reflective coating layer. The via hole pattern is thereafter etched through the anti-reflective coating layer, the dielectric layer, and the etch stop layer to form a via hole. A sacrificial via fill layer is filled in the via hole. A second patterned photoresist layer having a trench pattern is formed above the sacrificial via fill layer. The trench pattern is etched into the sacrificial via fill layer, the anti-reflective coating layer, and the dielectric layer to form a trench. The sacrificial via fill layer is removed in the via hole.

Abstract: A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes CO2 and ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.

Abstract: Via hole and trench structures and fabrication methods are disclosed. The structure comprises a conductive layer in a dielectric layer, and a via hole in the dielectric layer for exposing a portion of a surface of the conductive layer. A conductive liner covers the exposed surface of the first conductive layer. A trench is formed on the via hole in the dielectric without the conductive liner layer in the trench. Dual damascene structures and fabrications methods are also disclosed. Following the fabrication methods of the via hole and trench structures, a conductive layer is further formed in the via hole and trench structures.

Abstract: A method for cleaning semiconductor substrates includes a DI water clean operation that uses a spin speed no greater than 350 rpm. The cleaning method may include additional cleaning operations such as an organic clean, an aqueous chemical clean or a DI water/ozone clean. The cleaning method may be used to clean substrates after the conclusion of an etching procedure which exposes a single film between a Cu-containing conductive material and the environment. The spin speed of the DI water clean operation prevents copper corrosion due to breakdown of the film that separates the Cu-containing conductive material from the environment.

Abstract: An optical transceiver module includes an outer cage, a socket member, a locking mechanism, and a release mechanism. The socket member is disposed removably in the outer cage. The locking mechanism is provided on the outer cage and the socket member, and serves to lock releasably the socket member to the outer cage. The release mechanism is mounted rotatably on the socket member, and is formed with a wedge part that is in sliding engagement with the locking mechanism such that rotation of the wedge part of the release mechanism relative to the socket member drives the locking mechanism between a locking state, where the socket member is locked to the outer cage, and an unlocking state, where the socket member is removable from the outer cage.

Abstract: A method for fabricating dual damascene structures having improved IC performance and reduced RC delay characteristics is provided. In one embodiment, a substrate with an etch stop layer formed thereon is provided. A dielectric layer is formed on the etch stop layer and an anti-reflective coating layer is formed on the dielectric layer. A first patterned photoresist layer having a via hole pattern is formed on the anti-reflective coating layer. The via hole pattern is thereafter etched through the anti-reflective coating layer, the dielectric layer, and the etch stop layer to form a via hole. A sacrificial via fill layer is filled in the via hole. A second patterned photoresist layer having a trench pattern is formed above the sacrificial via fill layer. The trench pattern is etched into the sacrificial via fill layer, the anti-reflective coating layer, and the dielectric layer to form a trench. The sacrificial via fill layer is removed in the via hole.

Abstract: A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes CO2 and ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.

Abstract: Compounds that competitively inhibit binding of CSP to S. mutans histidine kinase are provided. The compounds are preferably a peptide or an antibody, and are preferably a derivative of [SEQ ID NO:2], a fragment of [SEQ ID NO:2] or a derivative of a fragment of [SEQ ID NO:2]. Methods of making these compounds and their use for inhibiting the growth of S. mutans, for inhibiting dental caries, and for improving dental health are also disclosed.

Abstract: A method for cleaning semiconductor substrates includes a DI water clean operation that uses a spin speed no greater than 350 rpm. The cleaning method may include additional cleaning operations such as an organic clean, an aqueous chemical clean or a DI water/ozone clean. The cleaning method may be used to clean substrates after the conclusion of an etching procedure which exposes a single film between a Cu-containing conductive material and the environment. The spin speed of the DI water clean operation prevents copper corrosion due to breakdown of the film that separates the Cu-containing conductive material from the environment.

Abstract: A method for improving a photolithographic patterning process to avoid undeveloped photoresist contamination in a semiconductor manufacturing process including providing a first semiconductor feature having an anisotropically etched opening including sidewalls. The first semiconductor feature further provide an overlying photoresist layer photolithographically patterned for anisotropically etching a second semiconductor feature opening overlying and encompassing the first semiconductor feature; blanket depositing a polymeric passivation layer over the overlying photoresist layer including covering at least a portion of the sidewalls including polymeric containing residues; and, removing the polymeric passivation layer including a substantial portion of the polymeric containing residues from at least a portion of the sidewalls prior to anisotropically etching the second semiconductor feature.

Abstract: A method for forming a metal filled semiconductor feature with improved structural stability including a semiconductor wafer having an anisotropically etched opening formed through a plurality of dielectric insulating layers revealing a first etching resistant layer overlying a conductive area; a plurality of dielectric insulating layers sequentially stacked to have alternating etching rates to a preferential etching process; subjecting the anisotropically etched opening to the preferential etching process whereby the sidewalls of the anisotropically etched opening are preferentially etched to produce etched dielectric insulating layers to form roughened sidewall surfaces; anisotropically etching through the etching resistant layer to reveal the conductive area; and, filling the anisotropically etched opening with a metal to form a metal filled semiconductor feature.

Abstract: A method for plasma etching a semiconductor feature to improve an etching profile including providing a semiconductor wafer including a photoresist layer having a photolithographically patterned portion for etching a feature through a thickness portion of at least one underlying dielectric layer; and, plasma treating the photoresist layer with a carbon monoxide (CO) containing plasma to induce a polymeric cross-linking reaction at the photoresist layer surface to decrease a photoresist layer etching rate in a subsequent etching process; and, etching said feature through the thickness portion to maintain a width dimension of said feature including the photolithographically patterned portion within a pre-determined dimensional variation.