Abstract: A method comprises forming a gate structure over a semiconductor substrate; forming an etch stop layer over the gate structure and an ILD layer over the etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer into the etch stop layer, resulting in a sidewall of the etch stop layer being exposed in the gate contact opening; oxidizing the exposed sidewall of the etch stop layer; after oxidizing the exposed sidewall of the etch stop layer, performing a second etching process to deepen the gate contact opening; and forming a gate contact in the deepened gate contact opening.

Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a metal gate stack over a substrate and an epitaxial structure over the substrate. The semiconductor device structure also includes a conductive contact electrically connected to the epitaxial structure. A topmost surface of the metal gate stack is vertically disposed between a topmost surface of the conductive contact and a bottommost surface of the conductive contact. The semiconductor device structure further includes a first conductive via electrically connected to the metal gate stack. The topmost surface of the conductive contact is vertically disposed between a topmost surface of the first conductive via and a bottommost surface of the first conductive via. In addition, the semiconductor device structure includes a second conductive via electrically connected to the conductive contact.

Abstract: Disclosed herein is a building assembly for assembling building panels. The building assembly includes a supporting member, a pair of a first sealing member, an elastically deformable gasket, and a second sealing member. The supporting member has a base, a channel disposed at the center of the base, and a pair of rails independently disposed next to the channel. The pair of a first sealing members independently includes a first base portion and two retention tongues independently extending outwardly from the first base portion. The elastically deformable gasket has a U- or V-shaped space in cross section and two flanges independently extending laterally from one edge of the U- or V-shaped space. The second sealing member has a second base portion and a rib disposed at the center of the second base portion.

Abstract: A method includes forming a conductive feature through a first dielectric layer, sequentially forming a second dielectric layer and a third dielectric layer over the first dielectric layer, and etching the third dielectric layer to form an opening. A first width of the opening at a top surface of the third dielectric layer is greater than a second width of the opening at a first interface between the third dielectric layer and the second dielectric layer. The method also includes etching the second dielectric layer until the opening extends to the conductive feature, thereby forming an enlarged opening, and forming a metal material in the enlarged opening. A third width of the enlarged opening at the first interface is equal to or less than a fourth width of the enlarged opening at a second interface between the second dielectric layer and the first dielectric layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first fin structure. The semiconductor device structure includes a first source/drain structure over the first fin structure. The semiconductor device structure includes a first dielectric layer over the first source/drain structure and the substrate. The semiconductor device structure includes a first conductive contact structure in the first dielectric layer and over the first source/drain structure. The semiconductor device structure includes a second dielectric layer over the first dielectric layer and the first conductive contact structure. The semiconductor device structure includes a first conductive via structure passing through the second dielectric layer and connected to the first conductive contact structure. The first conductive via structure has a first substantially strip shape in a top view of the first conductive via structure.

Abstract: Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block. The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.

Abstract: Embodiments include a contact structure and method of forming the same where the contact structure is deliberately positioned near the end of a metallic line. An opening is formed in an insulating structure positioned over the metallic line and then the opening is extended into the metallic line by an etching process. In the etching process, the line end forces etchant to concentrate back away from the line end, causing lateral etching of the extended opening. A subsequent contact is formed in the opening and enlarged opening.

Abstract: Improved conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.

Abstract: A method includes removing a dummy gate stack to form a first trench between gate spacers, forming a replacement gate stack in the first trench, recessing the replacement gate stack to form a second trench between the gate spacers, selectively depositing a conductive capping layer in the second trench, forming a dielectric hard mask in the second trench and over the conductive capping layer, and etching the dielectric hard mask using an etching gas to form an opening in the dielectric hard mask. The replacement gate stack is revealed to the opening. The conductive capping layer is more resistant to the etching gas than the replacement gate stack. The method further comprises forming a gate contact plug over and contacting the conductive capping layer.

Abstract: Disclosed herein is a building assembly for assembling building panels. The building assembly includes a supporting member, a pair of a first sealing member, an elastically deformable gasket, and a second sealing member. The supporting member has a base, a channel disposed at the center of the base, and a pair of rails independently disposed next to the channel. The pair of a first sealing members independently includes a first base portion and two retention tongues independently extending outwardly from the first base portion. The elastically deformable gasket has a U- or V-shaped space in cross section and two flanges independently extending laterally from one edge of the U- or V-shaped space. The second sealing member has a second base portion and a rib disposed at the center of the second base portion.

Abstract: A method comprises forming a gate structure over a semiconductor substrate; forming an etch stop layer over the gate structure and an ILD layer over the etch stop layer; performing a first etching process to form a gate contact opening extending through the ILD layer into the etch stop layer, resulting in a sidewall of the etch stop layer being exposed in the gate contact opening; oxidizing the exposed sidewall of the etch stop layer; after oxidizing the exposed sidewall of the etch stop layer, performing a second etching process to deepen the gate contact opening; and forming a gate contact in the deepened gate contact opening.

Abstract: A method comprises forming a source/drain contact over a source/drain region; forming an etch stop layer over the source/drain contact and an interlayer dielectric (ILD) layer over the etch stop layer; performing a first etching process to form a via opening extending though the ILD layer and a recess in the etch stop layer; oxidizing a sidewall of the recess in the etch stop layer; after oxidizing the sidewall of the recess in the etch stop layer, performing a second etching process to extend the via opening down to the source/drain contact; and after performing the second etching process, forming a source/drain via in the via opening.

Abstract: Disclosed herein are fabrics having different thermo-properties. The fabric is characterized in its structure by having a high melting temperature zone and a low melting temperature zone, which are respectively made up by yarns having high and low melting temperatures By having yarns of high and low temperatures in the fabric, in which the respective melting temperatures in the high and low melting temperature zones differ by about 30° C. to 150° C.; and the low melting temperature zone melts and eventually becomes harden after heat-activation, while the high melting temperature zone remains un-melted and soft after heat-activation.

Abstract: Disclosed herein is a mobile plastic recycling system mounted in a vehicle. The system is configured to process a plastic article and make it into thermoplastic items. The mobile plastic recycling system includes a plastic recycling apparatus and a power supply apparatus that are electrically coupled with each other; the system also includes a vehicle configured to carry and transport the power supply apparatus and plastic recycling apparatus.

Abstract: Disclosed herein are composite laminated articles and methods for manufacturing the same. According to some embodiments, the composite laminated article includes a polyethylene terephthalate (PET) fiber fabric layer, a PET nonwoven laminated board, and a PET film interposed between the PET fiber fabric layer and the PET nonwoven laminated board. In some embodiments, the composite laminated article further includes a low-density PET nonwoven fabric layer interposed between the PET film and the PET nonwoven laminated board. According to embodiments of the present disclosure, the composite laminated article is free of any thermoset binder, and hence, the composite laminated article is one hundred percent recyclable.

Abstract: Disclosed herein is a mobile plastic recycling system mounted in a vehicle. The system is configured to process a plastic article and make it into thermoplastic items. The mobile plastic recycling system includes a plastic recycling apparatus and a power supply apparatus that are electrically coupled with each other; the system also includes a vehicle configured to carry and transport the power supply apparatus and plastic recycling apparatus.

Abstract: Disclosed herein is a supporting assembly that allows easy assembly of a furniture. The supporting assembly includes structures that employ easy-to-use locking mechanism so that a user may assemble a furniture at desirable configuration without using a tool.

Abstract: A real-time fault detection and classification (FDC) system, which is in use with a semiconductor fabrication process having a first sub-fabrication process and a second sub-fabrication process, includes a computer integrated manufacturing (CIM) host adopting a SEMI equipment communication standard (SECS), a semiconductor tool for executing the first sub-fabrication process and generating first status data in conformity with the SECS, a non-semiconductor tool for executing the second sub-fabrication process and generating second status data in conformity with a predetermined connectivity standard different from the SECS, and a tool simulator connecting the tool simulator with the semiconductor tool and the non-semiconductor tool for receiving the first and second status data and transforming the second status data into third status data in conformity with the SECS such that the CIM host can classify the first and third status data according to a predetermined classification technique and get a control over eq

Abstract: A real-time fault detection and classification (FDC) system, which is in use with a semiconductor fabrication process having a first sub-fabrication process and a second sub-fabrication process, includes a computer integrated manufacturing (CIM) host adopting a SEMI equipment communication standard (SECS), a semiconductor tool for executing the first sub-fabrication process and generating first status data in conformity with the SECS, a non-semiconductor tool for executing the second sub-fabrication process and generating second status data in conformity with a predetermined connectivity standard different from the SECS, and a tool simulator connecting the tool simulator with the semiconductor tool and the non-semiconductor tool for receiving the first and second status data and transforming the second status data into third status data in conformity with the SECS such that the CIM host can classify the first and third status data according to a predetermined classification technique and get a control over eq

Abstract: An alarm analysis method capable of multi-purpose function. A plurality of efficiency indices are defined, including statistical-data-configuration, data-set, background-alarm-rate, peak-alarm-rate, active-alarm-distribution, bad-actors-identification, and alarm-report indices. A data warehouse is created according to the efficiency indices and using an online analytical processing method. A plurality of user interfaces are created according to the data warehouse and analysis results. The data warehouse is accessed using the user interfaces to retrieve the analysis results.