Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.

Abstract: This disclosure provides systems, methods, and devices for image processing that support enhanced white balancing operations. In a first aspect, a method of image processing includes receiving first image data obtained at a first aperture; determining a first output image frame based on the first image data by applying a first white balancing to at least a portion of the first image data; receiving second image data obtained at a second aperture; and determining a second output image frame based on the second image data by applying a second white balancing based on the first aperture and the second aperture to at least a portion of the second image data. The second white balancing may be based on a first compensation factor based on the first aperture and the second aperture used to adjust the first white balancing. Other aspects and features are also claimed and described.

Abstract: A power conversion system for converting an input power to an output power, includes: a current limit circuit clamping an input current of the output power to be not exceeding an input current limit during a current clamping state; and a charge quantity regulation circuit converting the output power to a temporary storage power in a temporary storage capacitor during a charging mode, wherein the charge quantity regulation circuit converts the temporary storage power to generate the output power in collaboration with the current limit circuit during a discharging mode. When the input current reaches a current threshold, the charge quantity regulation circuit enters the discharging mode. During the discharging mode, the charge quantity regulation circuit regulates an output voltage of the output power to a target level, wherein the target level is lower than an input voltage of the input power.

Abstract: A signal converting circuit includes a phase interpolator circuit and a bias voltage generation circuit. The phase interpolator circuit is configured to convert a plurality of input clock signals into an output clock signal according to a digital signal. The bias voltage generation circuit is electrically coupled to the phase interpolator circuit, is configured to generate a bias voltage according to a reference information and is configured to output the bias voltage to the phase interpolator circuit, so that the output clock signal has a predetermined phase corresponding to one of a plurality of bit configurations of the digital signal, wherein the reference information is relevant to a change of the phase interpolator circuit due to a temperature variation.

Abstract: A method includes following steps. A first transistor is formed on a substrate. A first dielectric layer is formed over the first transistor. A first trench is formed in the first dielectric layer. An amorphous semiconductor layer is deposited in the first trench and over the first dielectric layer. The amorphous semiconductor layer is crystallized into a crystalline semiconductor layer. A second transistor is formed over the crystalline semiconductor layer.

Abstract: A memory device is provided, including a memory array, a driver circuit, and recover circuit. The memory array includes multiple memory cells. Each memory cell is coupled to a control line, a data line, and a source line and, during a normal operation, is configured to receive first and second voltage signals. The driver circuit is configured to output at least one of the first voltage signal or the second voltage signal to the memory cells. The recover circuit is configured to output, during a recover operation, a third voltage signal, through the driver circuit to at least one of the memory cells. The third voltage signal is configured to have a first voltage level that is higher than a highest level of the first voltage signal or the second voltage signal, or lower than a lowest level of the first voltage signal or the second voltage signal.

Abstract: Some implementations described herein include operating components in a lithography system at variable speeds to reduce, minimize, and/or prevent particle generation due to rubbing of or collision between contact parts of the components. In some implementations, a component in a path of transfer of a semiconductor substrate in the lithography system is operated at a relatively high movement speed through a first portion of an actuation operation, and is operated at a reduced movement speed (e.g., a movement speed that is less than the high movement speed) through a second portion of the actuation operation in which contact parts of the component are to interact. The reduced movement speed reduces the likelihood of particle generation and/or release from the contact parts when the contact parts interact, while the high movement speed provides a high semiconductor substrate throughput in the lithography system.

Abstract: In a method of fabricating at least one IC, doped regions are formed on a semiconductor wafer using a first photolithography mask, including at least one doped region of a test structure. Active regions are formed on the semiconductor wafer using a second photolithography mask, including active regions of the test structure. Electrical contacts are formed on the active regions of the test structure. Electrical resistances are measured between pairs of active regions of the test structure using the electrical contacts. At least one metric is determined indicating whether the doped regions are spatially aligned with the active regions based on the measured electrical resistances. In response to the at least one metric indicating the doped regions are spatially aligned with the active regions, completing fabrication of the at least one integrated circuit.

Abstract: A portable electronic device including a first body, a second body, and a hinge mechanism is provided. The second body is connected to the first body through the hinge mechanism, and the hinge mechanism has a basis axis located at the first body and a rotation axis located at a lower end of the second body. When the second body rotates with respect to the first body, the rotation axis slides along an arc shaped path with respect to the basis axis to increase or decrease a distance between the rotation axis and the basis axis and increase or decrease a distance between the lower end of the second body and a back end of the first body.

Abstract: The present disclosure provides a semiconductor device with a plurality of semiconductor channel layers. The semiconductor channel layers include a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer. A strain in the second semiconductor layer is different from a strain in the first semiconductor layer. A gate is disposed over the plurality of semiconductor channel layers.

Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.

Abstract: An integrated circuit structure includes a substrate, a bottom nanostructure transistor, and a top nanostructure transistor. The bottom nanostructure transistor is over the substrate and includes a first channel layer, a first gate structure, and first source/drain epitaxial structures. The first gate structure wraps around the first channel layer. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The top nanostructure transistor is over the bottom nanostructure transistor and includes a second channel layer, a second gate structure, and second source/drain epitaxial structures. The second channel layer is over the first channel layer. The second gate structure wraps around the second channel layer. A bottom surface of the second gate structure is substantially coplanar with a bottom surface of the first gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer.

Abstract: A cell module is provided. The cell module includes a first substrate; a second substrate disposed opposite to the first substrate; a cell unit disposed between the first substrate and the second substrate; a first thermosetting resin layer disposed between the cell unit and the first substrate; a first protective layer disposed between the cell unit and the first thermosetting resin layer; and a second thermosetting resin layer disposed between the cell unit and the second substrate. The first protective layer includes a first polymer, wherein the cross-linking degree of the first polymer is 0 to 42.3%.

Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.

Abstract: A first and second patterned circuit layer are formed on a first surface and a second surface of a base material. A first adhesive layer is formed on the first patterned circuit layer. A portion of the first surface is exposed by the first patterned circuit layer. The metal reflection layer covers the first insulation layer and a reflectance thereof is greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer, and the first adhesive layer is disposed between the first patterned circuit layer and the first insulation layer. A transparent adhesive layer and a protection layer are formed on the metal reflection layer. The transparent adhesive layer is disposed between the metal reflection layer and the protection layer. The protection layer comprises a transparent polymer. The light transmittance is greater than or equal to 80%.

Abstract: A base material is provided. A first patterned circuit layer and a second patterned circuit layer are formed on a first surface and a second surface of the base material. A first insulation layer and a metal reflection layer are provided on the first patterned circuit layer and a portion of the first surface exposed by the first patterned circuit layer, wherein the metal reflection layer covers the first insulation layer, and a reflectance of the metal reflection layer is substantially greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer. A first ink layer is formed on the first insulation layer before the metal reflection layer is formed.

Abstract: An LED illumination device and a color temperature switching method thereof are provided. The LED illumination device includes a bridge rectifier chip, a microcontroller module, a first semiconductor switch module, a second semiconductor switch module, a first current limiting module, a second current limiting module, and a first light-emitting module and a second light-emitting module. The microcontroller module includes a microcontroller chip. The first semiconductor switch module includes a first semiconductor switch chip for receiving a first pulse width modulation signal output from the microcontroller chip. The second semiconductor switch module includes a second semiconductor switch chip for receiving a second pulse width modulation signal output from the microcontroller chip. When the AC power is supplied to the LED illumination device, the first and the second semiconductor switch modules are turned on and maintained within a predetermined turn-on percentage range without being completely turned off.

Abstract: A device comprise a first semiconductor channel layer over a substrate, a second semiconductor channel layer over the first semiconductor channel layer, and source/drain epitaxial structures on opposite sides of the first semiconductor channel layer and opposite sides of the second semiconductor channel layer. A compressive strain in the second semiconductor channel layer is greater than a compressive strain in the first semiconductor channel layer. The source/drain epitaxial structures each comprise a first region interfacing the first semiconductor channel layer and a second region interfacing the second semiconductor channel layer, and the first region has a composition different from a composition of the second region.

Abstract: A microbial carrier and a device for treating wastewater are provided. The microbial carrier includes a bacteriophilic material and a plurality of foam cells, wherein the foam cells are disposed in the bacteriophilic material. The bactericidal material is a reaction product of a composite, wherein the composition includes a hydrophobic polyvinyl alcohol and a cross-linking agent, wherein the surface energy of the hydrophobic polyvinyl alcohol is 30 mJ/m2 to 58 mJ/m2.

Abstract: A memory device includes a memory cell array and a memory controller. The memory cell array includes a plurality of memory blocks. Each of the memory blocks includes a plurality of word lines. A plurality of memory chunks is coupled to at least one of the word lines. The memory controller is configured to program data to a particular memory chunk of the plurality of memory chunks by performing a chunk operation that includes selecting a particular word line from the plurality of word lines, selecting a particular memory chunk from the plurality of memory chunks that are coupled to the particular word line, and applying a program voltage to a particular memory block corresponding to the particular memory chunk to program data to the particular memory chunk.