Abstract: A method includes following steps. A first transistor is formed on a substrate. A first dielectric layer is formed over the first transistor. A first trench is formed in the first dielectric layer. An amorphous semiconductor layer is deposited in the first trench and over the first dielectric layer. The amorphous semiconductor layer is crystallized into a crystalline semiconductor layer. A second transistor is formed over the crystalline semiconductor layer.

Abstract: A cell module is provided. The cell module includes a first substrate; a second substrate disposed opposite to the first substrate; a cell unit disposed between the first substrate and the second substrate; a first thermosetting resin layer disposed between the cell unit and the first substrate; a crosslinked polymer layer disposed between the cell unit and the first thermosetting resin layer; and a second thermosetting resin layer disposed between the cell unit and the second substrate. The crosslinked polymer layer includes a crosslinked polymer, and the crosslinked polymer has a crosslinking degree of from 35.4 to 67.4%.

Abstract: The present disclosure provides a semiconductor device with a plurality of semiconductor channel layers. The semiconductor channel layers include a first semiconductor layer and a second semiconductor layer disposed over the first semiconductor layer. A strain in the second semiconductor layer is different from a strain in the first semiconductor layer. A gate is disposed over the plurality of semiconductor channel layers.

Abstract: An integrated circuit structure includes a substrate, a bottom nanostructure transistor, and a top nanostructure transistor. The bottom nanostructure transistor is over the substrate and includes a first channel layer, a first gate structure, and first source/drain epitaxial structures. The first gate structure wraps around the first channel layer. The first source/drain epitaxial structures are on opposite sides of the first channel layer. The top nanostructure transistor is over the bottom nanostructure transistor and includes a second channel layer, a second gate structure, and second source/drain epitaxial structures. The second channel layer is over the first channel layer. The second gate structure wraps around the second channel layer. A bottom surface of the second gate structure is substantially coplanar with a bottom surface of the first gate structure. The second source/drain epitaxial structures are on opposite sides of the second channel layer.

Abstract: A cell module is provided. The cell module includes a first substrate; a second substrate disposed opposite to the first substrate; a cell unit disposed between the first substrate and the second substrate; a first thermosetting resin layer disposed between the cell unit and the first substrate; a first protective layer disposed between the cell unit and the first thermosetting resin layer; and a second thermosetting resin layer disposed between the cell unit and the second substrate. The first protective layer includes a first polymer, wherein the cross-linking degree of the first polymer is 0 to 42.3%.

Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.

Abstract: A first and second patterned circuit layer are formed on a first surface and a second surface of a base material. A first adhesive layer is formed on the first patterned circuit layer. A portion of the first surface is exposed by the first patterned circuit layer. The metal reflection layer covers the first insulation layer and a reflectance thereof is greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer, and the first adhesive layer is disposed between the first patterned circuit layer and the first insulation layer. A transparent adhesive layer and a protection layer are formed on the metal reflection layer. The transparent adhesive layer is disposed between the metal reflection layer and the protection layer. The protection layer comprises a transparent polymer. The light transmittance is greater than or equal to 80%.

Abstract: A base material is provided. A first patterned circuit layer and a second patterned circuit layer are formed on a first surface and a second surface of the base material. A first insulation layer and a metal reflection layer are provided on the first patterned circuit layer and a portion of the first surface exposed by the first patterned circuit layer, wherein the metal reflection layer covers the first insulation layer, and a reflectance of the metal reflection layer is substantially greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer. A first ink layer is formed on the first insulation layer before the metal reflection layer is formed.

Abstract: An LED illumination device and a color temperature switching method thereof are provided. The LED illumination device includes a bridge rectifier chip, a microcontroller module, a first semiconductor switch module, a second semiconductor switch module, a first current limiting module, a second current limiting module, and a first light-emitting module and a second light-emitting module. The microcontroller module includes a microcontroller chip. The first semiconductor switch module includes a first semiconductor switch chip for receiving a first pulse width modulation signal output from the microcontroller chip. The second semiconductor switch module includes a second semiconductor switch chip for receiving a second pulse width modulation signal output from the microcontroller chip. When the AC power is supplied to the LED illumination device, the first and the second semiconductor switch modules are turned on and maintained within a predetermined turn-on percentage range without being completely turned off.

Abstract: A device comprise a first semiconductor channel layer over a substrate, a second semiconductor channel layer over the first semiconductor channel layer, and source/drain epitaxial structures on opposite sides of the first semiconductor channel layer and opposite sides of the second semiconductor channel layer. A compressive strain in the second semiconductor channel layer is greater than a compressive strain in the first semiconductor channel layer. The source/drain epitaxial structures each comprise a first region interfacing the first semiconductor channel layer and a second region interfacing the second semiconductor channel layer, and the first region has a composition different from a composition of the second region.

Abstract: A microbial carrier and a device for treating wastewater are provided. The microbial carrier includes a bacteriophilic material and a plurality of foam cells, wherein the foam cells are disposed in the bacteriophilic material. The bactericidal material is a reaction product of a composite, wherein the composition includes a hydrophobic polyvinyl alcohol and a cross-linking agent, wherein the surface energy of the hydrophobic polyvinyl alcohol is 30 mJ/m2 to 58 mJ/m2.

Abstract: A hydrophobic polyvinyl alcohol and a method for preparing hydrophobic polyvinyl alcohol are provided. The hydrophobic polyvinyl alcohol includes a first repeat unit represented by Formula (I), a second repeat unit represented by Formula (II), and a third repeat unit represented by Formula (III) wherein R1 is —Si(R2)3, R2 is independently C1-6 alkoxy group, C6-18 alkyl group, or C6-22 alkenyl group, and at least one R2 is C6-18 alkyl group or C6-22 alkenyl group; R3 and R4 are independently C6-18 alkyl group or C6-22 alkenyl group; j is 3 to 7; and k is 1 to 30.

Abstract: A memory device includes a memory cell array and a memory controller. The memory cell array includes a plurality of memory blocks. Each of the memory blocks includes a plurality of word lines. A plurality of memory chunks is coupled to at least one of the word lines. The memory controller is configured to program data to a particular memory chunk of the plurality of memory chunks by performing a chunk operation that includes selecting a particular word line from the plurality of word lines, selecting a particular memory chunk from the plurality of memory chunks that are coupled to the particular word line, and applying a program voltage to a particular memory block corresponding to the particular memory chunk to program data to the particular memory chunk.

Abstract: A device comprises a plurality of nanosheets, source/drain stressors, and a gate structure wrapping around the nanosheets. The nanosheets extend in a first direction above a semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors comprises a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of a Group IV element and a Group V element. An atomic ratio of the Group V element to the Group IV element in the second epitaxial layer is greater than an atomic ratio of the Group V element to the Group IV element in the first epitaxial layer.

Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.

Abstract: A microbial carrier and a device for treating wastewater are provided. The microbial carrier includes a bacteriophilic material and a plurality of foam cells, wherein the foam cells are disposed in the bacteriophilic material. The bactericidal material is a reaction product of a composite, wherein the composition includes a hydrophobic polyvinyl alcohol and a cross-linking agent, wherein the surface energy of the hydrophobic polyvinyl alcohol is 30 mJ/m2 to 58 mJ/m2.

Abstract: A solar cell module is provided. The solar cell module includes a first substrate, a second substrate opposite the first substrate, a cell unit disposed between the first and second substrates, a first thermosetting resin layer disposed between the cell unit and the first substrate, a first thermoplastic resin layer disposed between the cell unit and the first thermosetting resin layer, a second thermosetting resin layer disposed between the cell unit and the second substrate, and a second thermoplastic resin layer disposed between the cell unit and the second thermosetting resin layer.

Abstract: A hydrophobic polyvinyl alcohol and a method for preparing hydrophobic polyvinyl alcohol are provided. The hydrophobic polyvinyl alcohol includes a first repeat unit represented by Formula (I), a second repeat unit represented by Formula (II), and a third repeat unit represented by Formula (III) wherein R1 is —Si(R2)3, R2 is independently C1-6 alkoxy group, C6-18 alkyl group, or C6-22 alkenyl group, and at least one R2 is C6-18 alkyl group or C6-22 alkenyl group; R3 and R4 are independently C6-18 alkyl group or C6-22 alkenyl group; j is 3 to 7; and k is 1 to 30.

Abstract: Systems, methods, and apparatus including computer-readable mediums for managing open blocks in memory systems such as NAND flash memory devices are provided. In one aspect, a method includes: evaluating a read disturbance level of an open block in a memory, the open block having one or more programmed word lines and one or more blank word lines, and in response to determining that the read disturbance level of the open block is beyond a threshold level, managing each memory cell in at least one of the blank word lines to have a smaller data storing capacity than each memory cell in at least one of the one or more programmed word lines so as to reduce impact of read disturbance.

Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.