Patents by Inventor Yi Fan

Yi Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200110532
    Abstract: A method and system of providing a control user interface at a first home appliance are disclosed, the method including detecting presence of a user within a threshold range of the first home appliance, and performing image processing on one or more real-time images of the user to determine one or more characteristics of a facial image of the user; determining at least a first parameter that is configured to trigger a first change in a current control user interface configuration for the first home appliance; and activating a first control user interface configuration corresponding to the first parameter for the first home appliance while the presence of the first user continues to be detected within the threshold range of the first home appliance.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 9, 2020
    Inventors: Suresh Mani, Yi Fan, Zhicai Ou
  • Publication number: 20200105885
    Abstract: A first dummy gate and a second dummy gate are formed on a substrate with a gap between the first and second dummy gates. The first dummy gate has a first sidewall. The second dummy gate has a second sidewall directly facing the first sidewall. A first sidewall spacer is disposed on the first sidewall. A second sidewall spacer is disposed on the second sidewall. A contact etch stop layer is deposited on the first and second dummy gates and on the first and second sidewall spacers. The contact etch stop layer is subjected to a tilt-angle plasma etching process to trim a corner portion of the contact etch stop layer. An inter-layer dielectric layer is then deposited on the contact etch stop layer and into the gap.
    Type: Application
    Filed: December 2, 2019
    Publication date: April 2, 2020
    Inventors: Yi-Fan Li, Kuo-Chin Hung, Wen-Yi Teng, Ti-Bin Chen
  • Publication number: 20200103717
    Abstract: An information handling system may comprise a liquid crystal display having a plurality of pixels, an electrochromic material layer having a plurality of electrodes disposed between an interior surface of a chassis and a transistor-array layer, and a high reflection layer reflecting light emitted from an LED disposed between the electrochromic material layer and the transistor-array layer away from the interior surface of the chassis. A processor may execute code instructions of an electrochromic material regional backlight unit dimming control system to identify a low-intensity pixel region including a subset of the plurality of pixels associated within high dynamic ratio image data with a low intensity value, identify an electrode of the electrochromic material layer associated with the low-intensity pixel region; and pass a current through the electrode such that a portion of the electrochromic material becomes opaque to the light reflected from the high reflection layer.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 2, 2020
    Applicant: Dell Products, LP
    Inventors: Ching-Feng Chen, Meng-Feng Hung, Yi Fan Wang, Tsung-Chin Cheng, Pavel Sergei Olchovik
  • Patent number: 10601116
    Abstract: A wireless terminal is disclosed. The wireless terminal includes a first antenna, a second antenna, a printed circuit board, a bracket, and a resonator. The first antenna is located at one side of the printed circuit board. The second antenna is located at another side of the printed circuit board. The printed circuit board functions as a metal ground of the first antenna and the second antenna. The resonator is located on the bracket. A ground point of the resonator is located on the printed circuit board. A clearance exists between the resonator and the printed circuit board.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: March 24, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Liang Zhao, Hanyang Wang, Qing Liu, Huiliang Xu, Yi Fan, Yao Lan, Zhongying Long, Dongxing Tu
  • Publication number: 20200079767
    Abstract: Provided are novel compounds of Formula (I): pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof, which are useful in the treatment of diseases and disorders mediated by ROR?. Also provided are pharmaceutical compositions comprising the novel compounds of Formula (I) and methods for their use in treating one or more inflammatory, metabolic, autoimmune and other diseases or disorders.
    Type: Application
    Filed: April 25, 2019
    Publication date: March 12, 2020
    Inventors: David A. Claremon, Lawrence Wayne Dillard, Chengguo Dong, Yi Fan, Stephen D. Lotesta, Andrew Marcus, Suresh B. Singh, Colin M. Tice, Jing Yuan, Wei Zhao, Linghang Zhuang
  • Publication number: 20200062707
    Abstract: Provided are novel compounds of Formula I: pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof, which are useful in the treatment of diseases and disorders mediated by RORy. Also provided are pharmaceutical compositions comprising the novel compounds of Formula I and methods for their use in treating one or more inflammatory, metabolic, autoimmune and other diseases or disorders.
    Type: Application
    Filed: April 3, 2019
    Publication date: February 27, 2020
    Inventors: David A. Claremon, Lawrence Wayne Dillard, Yi Fan, Stephen D. Lotesta, Suresh B. Singh, Colin M. Tice, Wei Zhao, Linghang Zhuang
  • Publication number: 20200057342
    Abstract: A system comprising a display, a display cover, a plurality of sensors disposed between the display and the display cover and a lighting control system coupled to the display and the plurality of sensors, the lighting control system configured to receive one or more signals from the plurality of sensors and to reduce a backlight level of a subgroup of lighting elements associated with the one or more sensors associated with the one or more signals, wherein the subgroup of lighting elements is one of a plurality of subgroups of lighting elements of the display.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Applicant: DELL PRODUCTS L.P.
    Inventors: Ching-Feng Chen, Meng-Feng Hung, Yu-Lung Lin, Yi-Fan Wang, Wei-Sung Lin
  • Publication number: 20200054157
    Abstract: A paper straw has an inner tube, an outer tube, and a pattern portion. The inner tube and the outer tube are both tubular bodies formed by spirally winding paper sheets. The pattern portion is disposed between the inner tube and the outer tube. The paper sheets that are used to wind the inner tube and the outer tube have light-transmissive properties. Then the pattern portion can be externally displayed through the outer tube or the inner tube, and this can avoid the pattern portion directly contacting food or human body.
    Type: Application
    Filed: July 23, 2019
    Publication date: February 20, 2020
    Inventors: Chia Lun Wu, Szu I Wu, Po Tsun Wu, Yi Fan Hsu, Chih Chia Liu, Tsai Yu Wu
  • Patent number: 10541309
    Abstract: A semiconductor structure is disclosed. The semiconductor structure includes first and second metal gates on a substrate with a gap therebetween. The first metal gate has a first sidewall, and the second metal gate has a second sidewall directly facing the first sidewall. A contact etch stop layer (CESL) is disposed within the gap and extends along the first and second sidewalls. The CESL has a first top portion adjacent to a top surface of the first metal gate and a second top portion adjacent to a top surface of the second metal gate. The first top portion and the second top portion have a trapezoid cross-sectional profile. A first sidewall spacer is disposed on the first sidewall and between the CESL and the first metal gate. A second sidewall spacer is disposed on the second sidewall and between the CESL and the second metal gate.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: January 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP
    Inventors: Yi-Fan Li, Kuo-Chin Hung, Wen-Yi Teng, Ti-Bin Chen
  • Patent number: 10535557
    Abstract: A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The HT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsan-Chun Wang, De-Wei Yu, Ziwei Fang, Yi-Fan Chen
  • Publication number: 20200013623
    Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 9, 2020
    Inventors: Hongfa Luan, Yi-Fan Chen, Chun-Yen Peng, Cheng-Po Chau, Wen-Yu Ku, Huicheng Chang
  • Publication number: 20200006517
    Abstract: A structure of semiconductor device includes a gate structure, disposed on a substrate. A spacer is disposed on a sidewall of the gate structure, wherein the spacer is an l-like structure. A first doped region is disposed in the substrate at two sides of the gate structure. A second doped region is disposed in the substrate at the two sides of the gate structure, overlapping the first doped region. A silicide layer is disposed on the substrate within the second doped region, separating from the spacer by a distance. A dielectric layer covers over the second doped region and the gate structure with the spacer.
    Type: Application
    Filed: August 2, 2018
    Publication date: January 2, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Yi-Fan Li, Po-Ching Su, Cheng-Chia Liu, Yen-Tsai Yi, Wei-Chuan Tsai, Chih-Chiang Wu, Ti-Bin Chen, Ching-Chu Tseng
  • Patent number: 10504735
    Abstract: Embodiment described herein provide a thermal treatment process following a high-pressure anneal process to keep hydrogen at an interface between a channel region and a gate dielectric layer in a field effect transistor while removing hydrogen from the bulk portion of the gate dielectric layer. The thermal treatment process can reduce the amount of threshold voltage shift caused by a high-pressure anneal. The high-pressure anneal and the thermal treatment process may be performed any time after formation of the gate dielectric layer, thus, causing no disruption to the existing process flow.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hongfa Luan, Huicheng Chang, Cheng-Po Chau, Wen-Yu Ku, Yi-Fan Chen, Chun-Yen Peng
  • Publication number: 20190362666
    Abstract: A display panel includes a plurality of data lines and a multiplexer circuit including a first switch set and a second switch set each having a plurality of switches. Each switch of the switch sets has a first end connected to the data lines and a second end. The second ends of a same switch set are connected to each other to form a receiving end connected to a data signal source. The first switch set is turned on alternately by a first clock signal and a second clock signal. The second switch set is turned alternately by a third clock signal and a fourth clock signal. The enabling period of the first clock signal and that of the third clock signal partially overlap and have asynchronous starting times. The enabling period of the second clock signal and that of the fourth clock signal at least partially overlap.
    Type: Application
    Filed: May 22, 2019
    Publication date: November 28, 2019
    Inventors: Shao-Ting Chen, Yi-Fan Lin
  • Publication number: 20190352286
    Abstract: Provided are novel compounds of Formula I: pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof, which are useful in the treatment of diseases and disorders mediated by RORy. Also provided are pharmaceutical com-positions comprising the novel compounds of Formula I and methods for their use in treating one or more inflammatory, metabolic, autoimmune and other diseases or disorders.
    Type: Application
    Filed: January 27, 2017
    Publication date: November 21, 2019
    Inventors: David A. Claremon, Lawrence Wayne Dillard, Yi Fan, Stephen D. Lotesta, Suresh B. Singh, Colin M. Tice, Wei Zhao, Linghang Zhuang
  • Publication number: 20190353170
    Abstract: A method for controlling a fan in a fan start-up stage including a first time period and a second time period comprises the following steps of: during the first time period, continuously providing a first driving signal to drive the fan; and during the second time period, continuously providing a second driving signal to drive the fan; wherein, during the first time period the signal value (driving energy) of the first driving signal gradually decreases until being equal to the signal value of the second driving signal, and the signal value of the first driving signal is initially greater than the signal value of the second driving signal. A fan is also disclosed.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 21, 2019
    Inventors: Yi-Fan LIN, Chung-Hung TANG, Cheng-Chieh LIU, Chun-Lung CHIU
  • Publication number: 20190339886
    Abstract: A distributed storage system includes multiple partitions. A block received for storage is striped across the partitions if it meets predetermined criteria. Multiple tables are maintained for indexing the blocks and the subblocks of blocks that are partitioned. The tables for the subblocks and the tables for the corresponding blocks of the subblocks are updated to include metadata for the subblocks for retrieving the subblocks in response to a request for a corresponding stored block.
    Type: Application
    Filed: February 19, 2019
    Publication date: November 7, 2019
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Jegan DEVARAJU, Pradeep Seela, Yi-Fan Tsai, Yongfu Lou, Kristopher T. Lange, Pei Zhang, Maneesh Sah, Shane K. Mainali
  • Publication number: 20190340185
    Abstract: Data is replicated between primary and secondary storage systems using a data pulling process or a log shipping process. If data is to be replicated through the log shipping process, a transaction and its associated data get stored in a transaction log in the secondary storage system. Subsequently, when the transaction gets executed, actual data gets persisted from the transaction log to a data log in the secondary storage system. If the data is to be replicated through the data pulling process, the transaction is stored in the transaction log. However, the associated data for the transaction is retrieved from the first primary storage system and stored directly in the data log in the secondary system.
    Type: Application
    Filed: March 21, 2019
    Publication date: November 7, 2019
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Pradeep Seela, Pei Zhang, Yongfu Lou, Jegan Devaraju, Krishnan Varadarajan, Yi-Fan Tsai, Maneesh Sah, Kristopher T. Lange, Shane K. Mainali
  • Publication number: 20190322687
    Abstract: Provided are novel compounds of Formula I: pharmaceutically acceptable salts thereof, and pharmaceutical compositions thereof, which are useful in the treatment of diseases and disorders mediated by ROR?. Also provided are pharmaceutical compositions comprising the novel compounds of Formula I and methods for their use in treating one or more inflammatory, metabolic, autoimmune and other diseases or disorders.
    Type: Application
    Filed: November 17, 2016
    Publication date: October 24, 2019
    Applicant: Vitae Pharmaceuticals, LLC
    Inventors: David A. Claremon, Lawrence Wayne Dillard, Yi Fan, Lanqi Jia, Suresh B. Singh, Colin M. Tice, Zhenrong Xu, Jing Yuan, Linghang Zhuang
  • Patent number: 10446447
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a liner on the fin-shaped structure; and removing the liner and part of the fin-shaped structure so that a sidewall of the fin-shaped structure comprises a curve. Moreover, the method includes forming an epitaxial layer around the sidewall of the fin-shaped structure while a top surface of the fin-shaped structure is exposed.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, I-Cheng Hu, Chun-Jen Chen, Tien-I Wu, Yu-Shu Lin, Chun-Yuan Wu