Patents by Inventor Yi-Fang Pai

Yi-Fang Pai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10861935
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-I Kuo, Shao-Fu Fu, Chia-Ling Chan, Yi-Fang Pai, Li-Li Su, Wei Hao Lu, Wei Te Chiang, Chii-Horng Li
  • Publication number: 20200350432
    Abstract: An integrated circuit includes a gate structure over a substrate. The integrated circuit includes a first silicon-containing material structure in a recess. The first silicon-containing material structure includes a first layer below a top surface of the substrate and in direct contact with the substrate. The first silicon-containing material structure includes a second layer over the first layer, wherein an entirety of the second layer is above the top surface of the substrate, a first region of the second layer closer to the gate structure is thinner than a second region of the second layer farther from the gate structure. The first silicon-containing material structure includes a third layer between the first layer and the second layer, wherein at least a portion of the third layer is below the top surface of the substrate.
    Type: Application
    Filed: July 20, 2020
    Publication date: November 5, 2020
    Inventors: Shih-Hsien HUANG, Yi-Fang PAI, Chien-Chang SU
  • Patent number: 10734517
    Abstract: The integrated circuit includes a gate structure over a substrate. The integrated circuit further includes a first silicon-containing material structure in a recess adjacent to the gate structure. The first silicon-containing material structure includes a first layer having an uppermost surface below a top surface of the substrate and a bottommost surface in contact with the substrate. The first silicon-containing material structure further includes a second layer over the first layer, wherein an entirety of the second layer is co-planar with or above the top surface of the substrate. A first region of the second layer closer to the gate structure is thicker than a second region of the second layer farther from the gate structure. Thickness is measured in a direction perpendicular to the top surface of the substrate.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hsien Huang, Yi-Fang Pai, Chien-Chang Su
  • Publication number: 20190355816
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.
    Type: Application
    Filed: August 5, 2019
    Publication date: November 21, 2019
    Inventors: Chien-I Kuo, Shao-Fu Fu, Chia-Ling Chan, Yi-Fang Pai, Li-Li Su, Wei Hao Lu, Wei Te Chiang, Chii-Horng Li
  • Patent number: 10374038
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: August 6, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-I Kuo, Chii-Horng Li, Chia-Ling Chan, Li-Li Su, Yi-Fang Pai, Wei Te Chiang, Shao-Fu Fu, Wei Hao Lu
  • Patent number: 10340190
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure and a second fin structure over a substrate. The semiconductor device structure also includes a gate structure over the first and second fin structure. The semiconductor device structure further includes a source/drain structure over the first and second fin structure. The source/drain structure includes a first semiconductor layer over the first fin structure and a second semiconductor layer over the second fin structure. The source/drain structure also includes a third semiconductor layer covering the first and second semiconductor layers. The third semiconductor layer has a surface with [110] plane orientation.
    Type: Grant
    Filed: November 24, 2017
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Hao Lu, Yi-Fang Pai, Tuoh-Bin Ng, Li-Li Su, Chii-Horng Li
  • Publication number: 20190164835
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure and a second fin structure over a substrate. The semiconductor device structure also includes a gate structure over the first and second fin structure. The semiconductor device structure further includes a source/drain structure over the first and second fin structure. The source/drain structure includes a first semiconductor layer over the first fin structure and a second semiconductor layer over the second fin structure. The source/drain structure also includes a third semiconductor layer covering the first and second semiconductor layers. The third semiconductor layer has a surface with [110] plane orientation.
    Type: Application
    Filed: November 24, 2017
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Hao LU, Yi-Fang PAI, Tuoh-Bin NG, Li-Li SU, Chii-Horng LI
  • Publication number: 20190165100
    Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.
    Type: Application
    Filed: March 15, 2018
    Publication date: May 30, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-I KUO, Chii-Horng LI, Chia-Ling CHAN, Li-Li SU, Yi-Fang PAI, Wei Te CHIANG, Shao-Fu FU, Wei Hao LU
  • Patent number: 10134896
    Abstract: A semiconductor substructure with an improved source/drain structure is described. The semiconductor substructure can include an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structure is disposed over or on a recess surface of a recess that extends below said upper surface. The source/drain structure includes a first epitaxial layer, having a first composition, over or on the interface surface, and a subsequent epitaxial layer, having a subsequent composition, over or on the first epitaxial layer. A dopant concentration of the subsequent composition is greater than a dopant concentration of the first composition, and a carbon concentration of the first composition ranges from 0 to 1.4 at.-%. Methods of making semiconductor substructures including improved source/drain structures are also described.
    Type: Grant
    Filed: March 1, 2013
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun Hsiung Tsai, Sheng-Wen Yu, Ying-Min Chou, Yi-Fang Pai
  • Patent number: 9997631
    Abstract: A method of forming a semiconductor device includes forming a fin on a substrate and forming a source/drain region on the fin. The method further includes forming a doped metal silicide layer on the source/drain region and forming a super-saturated doped interface between the doped metal silicide and the source/drain region. An example benefit includes reduction of contact resistance between metal silicide layers and source/drain regions.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
    Inventors: Cheng-Yu Yang, Kai-Hsuan Lee, Sheng-Chen Wang, Sai-Hooi Yeong, Yi-Fang Pai, Yen-Ming Chen
  • Publication number: 20180033887
    Abstract: The integrated circuit includes a gate structure over a substrate. The integrated circuit further includes a first silicon-containing material structure in a recess adjacent to the gate structure. The first silicon-containing material structure includes a first layer having an uppermost surface below a top surface of the substrate and a bottommost surface in contact with the substrate. The first silicon-containing material structure further includes a second layer over the first layer, wherein an entirety of the second layer is co-planar with or above the top surface of the substrate. A first region of the second layer closer to the gate structure is thicker than a second region of the second layer farther from the gate structure. Thickness is measured in a direction perpendicular to the top surface of the substrate.
    Type: Application
    Filed: October 6, 2017
    Publication date: February 1, 2018
    Inventors: Shih-Hsien HUANG, Yi-Fang PAI, Chien-Chang SU
  • Publication number: 20170352762
    Abstract: A method of forming a semiconductor device includes forming a fin on a substrate and forming a source/drain region on the fin. The method further includes forming a doped metal silicide layer on the source/drain region and forming a super-saturated doped interface between the doped metal silicide and the source/drain region. An example benefit includes reduction of contact resistance between metal silicide layers and source/drain regions.
    Type: Application
    Filed: August 2, 2016
    Publication date: December 7, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Yu YANG, Kai-Hsuan LEE, Sheng-Chen WANG, Sai-Hooi YEONG, Yi-Fang PAI, Yen-Ming CHEN
  • Patent number: 9786780
    Abstract: An integrated circuit includes a gate structure over a substrate. A silicon-containing material structure is in each of recesses that are adjacent to the gate structure. The silicon-containing material structure has a first region and a second region, the second region is closer to the gate structure than the first region, and the first region is thicker than the second region.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: October 10, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Hsien Huang, Yi-Fang Pai, Chien-Chang Su
  • Patent number: 9666691
    Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chang Su, Tsz-Mei Kwok, Hsien-Hsin Lin, Hsueh-Chang Sung, Yi-Fang Pai, Kuan-Yu Chen
  • Patent number: 9647115
    Abstract: A method of forming a semiconductor structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure from the fin structure; (iii) forming a sacrificial structure surrounding the epitaxy structure; (iv) forming a dielectric layer covering the sacrificial structure; (v) forming an opening passing through the dielectric layer to partially expose the sacrificial structure; (vi) removing a portion of the sacrificial structure to expose a portion of the epitaxy structure; and (vii) forming a contact structure in contact with the exposed portion of the epitaxy structure. A semiconductor structure is disclosed herein as well.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: May 9, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yasutoshi Okuno, Cheng-Long Chen, Meng-Chun Chang, Sung-Li Wang, Yi-Fang Pai, Yusuke Oniki
  • Publication number: 20170110578
    Abstract: A method of forming a semiconductor structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure from the fin structure; (iii) forming a sacrificial structure surrounding the epitaxy structure; (iv) forming a dielectric layer covering the sacrificial structure; (v) forming an opening passing through the dielectric layer to partially expose the sacrificial structure; (vi) removing a portion of the sacrificial structure to expose a portion of the epitaxy structure; and (vii) forming a contact structure in contact with the exposed portion of the epitaxy structure. A semiconductor structure is disclosed herein as well.
    Type: Application
    Filed: October 14, 2015
    Publication date: April 20, 2017
    Inventors: Yasutoshi OKUNO, Cheng-Long CHEN, Meng-Chun CHANG, Sung-Li WANG, Yi-Fang PAI, Yusuke ONIKI
  • Patent number: 9564509
    Abstract: A method of fabricating an integrated circuit device includes forming a first gate structure in a first region of a substrate and a second gate structure in a second region of the substrate. The method includes forming a protective layer overlying the first and the second gate structures. The method includes removing a portion of the protective layer over the second gate structure. The method includes forming features adjacent to the second gate structure. The method further includes forming a spacer over at least a portion of the features adjacent to the second gate structure, wherein the features separate the spacer from the substrate adjacent to the second gate structure. The method includes removing the second portion of the protective layer. Removing the second portion of the protective layer includes forming a protector over the second gate structure; and performing an etching process using a chemical comprising hydrofluoric acid (HF).
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: February 7, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Hsi Yeh, Hsien-Hsin Lin, Ying-Hsueh Chang Chien, Yi-Fang Pai, Chi-Ming Yang, Chin-Hsiang Lin
  • Patent number: 9537004
    Abstract: A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and forming a low diffusibility layer adjacent to the high diffusibility layer. After these two layers are formed, an anneal is performed to diffuse dopants from the high diffusibility layer underneath the gate stack to help form a channel region.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: January 3, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chii-Ming Wu, Chien-Chang Su, Hsien-Hsin Lin, Yi-Fang Pai
  • Patent number: 9443847
    Abstract: An integrated circuit includes a gate structure disposed over a substrate. The integrated circuit further includes a silicon-containing material structure disposed over a recess adjacent to the gate structure. The silicon-containing material structure includes a first epitaxial layer and a second epitaxial layer. A gate corner of the gate structure is free of dislocation and a corner of the second epitaxial layer away from a surface of the substrate and next to a spacer of the gate structure includes dislocations, wherein the dislocations are away from the gate corner.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: September 13, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun Hsiung Tsai, Yi-Fang Pai
  • Patent number: 9412870
    Abstract: A device includes a substrate and a recess in the substrate. The recess has a bottom and sidewalls. The device also includes a first epitaxial layer over the bottom of the recess, and a second epitaxial layer over the first epitaxial layer and over the sidewalls of the recess, the second epitaxial layer having a different lattice constant than the substrate. The device further includes a third epitaxial layer over the second epitaxial layer and filling the recess.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: King-Yuen Wong, Chia-Yu Lu, Chien-Chang Su, Yen-Chun Lin, Yi-Fang Pai, Da-Wen Lin