Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.

Abstract: An engineered epitaxial region compensates for short channel effects of a MOS device by providing a blocking layer to reduce or prevent dopant diffusion while at the same time reducing or eliminating the side effects of the blocking layer such as increased leakage current of a BJT device and/or decreased breakdown voltage of a rectifier. These side effects are reduced or eliminated by a non-conformal dopant-rich layer between the blocking layer and the substrate, which lessens the abruptness of the junction, thus lower the electric field at the junction region. Such a scheme is particularly advantageous for system on chip applications where it is desirable to manufacture MOS, BJT, and rectifier devices simultaneously with common process steps.

Abstract: An integrated circuit includes a gate structure disposed over a substrate. The integrated circuit further includes a silicon-containing material structure disposed over a recess adjacent to the gate structure. The silicon-containing material structure includes a first epitaxial layer and a second epitaxial layer. A gate corner of the gate structure is free of dislocation and a corner of the second epitaxial layer away from a surface of the substrate and next to a spacer of the gate structure includes dislocations, wherein the dislocations are away from the gate corner.

Abstract: A method of fabricating an integrated circuit device includes forming a first gate structure in a first region of a substrate and a second gate structure in a second region of the substrate. The method includes forming a protective layer overlying the first and the second gate structures. The method includes removing a portion of the protective layer over the second gate structure. The method includes forming features adjacent to the second gate structure. The method further includes forming a spacer over at least a portion of the features adjacent to the second gate structure, wherein the features separate the spacer from the substrate adjacent to the second gate structure. The method includes removing the second portion of the protective layer. Removing the second portion of the protective layer includes forming a protector over the second gate structure; and performing an etching process using a chemical comprising hydrofluoric acid (HF).

Abstract: Mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) are provided. The mechanisms eliminate dislocations near gate corners and gate corner defects (GCDs), and maintain transistor performance. The mechanisms described involve using a post-deposition etch to remove residual dislocations near gate corners after a cyclic deposition and etching (CDE) process is used to fill a portion of the recess regions with an epitaxially grown silicon-containing material. The mechanisms described also minimize the growth of dislocations near gate corners during the CDE process. The remaining recess regions may be filled by another silicon-containing layer deposited by an epitaxial process without forming dislocations near gate corners. The embodiments described enable gate corners to be free of dislocation defects, preserve the device performance from degradation, and widen the process window of forming S/D regions without gate corner defects and chamber matching issues.

Abstract: A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid.

Abstract: The present disclosure relates to a method of forming an epitaxial layer through asymmetric cyclic deposition etch (CDE) epitaxy. An initial layer growth rate of one or more cycles of the CDE process are designed to enhance a crystalline quality of the epitaxial layer. A growth rate of the epitaxial material may be altered by adjusting a flow rate of one or more silicon-containing precursors within a processing chamber wherein the epitaxial growth takes place. An etch rate may also be altered by adjusting a temperature or partial pressure of one or more vapor etchants, or the temperature within the processing chamber. In some embodiments, an initial layer thickness that is greater than a critical thickness of the epitaxial material for strain relaxation is achieved with a low growth rate, followed by a high growth rate for the remainder of epitaxial growth. Other methods are also disclosed.

Abstract: An integrated circuit includes a gate structure over a substrate. A silicon-containing material structure is in each of recesses that are adjacent to the gate structure. The silicon-containing material structure has a first region and a second region, the second region is closer to the gate structure than the first region, and the first region is thicker than the second region.

Abstract: The present disclosure relates to a method of forming an epitaxial layer through asymmetric cyclic deposition etch (CDE) epitaxy. An initial layer growth rate of one or more cycles of the CDE process are designed to enhance a crystalline quality of the epitaxial layer. A growth rate of the epitaxial material may be altered by adjusting a flow rate of one or more silicon-containing precursors within a processing chamber wherein the epitaxial growth takes place. An etch rate may also be altered by adjusting a temperature or partial pressure of one or more vapor etchants, or the temperature within the processing chamber. In some embodiments, an initial layer thickness that is greater than a critical thickness of the epitaxial material for strain relaxation is achieved with a low growth rate, followed by a high growth rate for the remainder of epitaxial growth. Other methods are also disclosed.

Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A silicon-containing material structure is formed in each of the recesses. The silicon-containing material structure has a first region and a second region, the second region is closer to the gate structure than the first region, and the first region is thicker than the second region.

Abstract: Mechanisms for forming source/drain (S/D) regions of field effect transistors (FETs) are provided. The mechanisms eliminate dislocations near gate corners and gate corner defects (GCDs), and maintain transistor performance. The mechanisms described involve using a post-deposition etch to remove residual dislocations near gate corners after a cyclic deposition and etching (CDE) process is used to fill a portion of the recess regions with an epitaxially grown silicon-containing material. The mechanisms described also minimize the growth of dislocations near gate corners during the CDE process. The remaining recess regions may be filled by another silicon-containing layer deposited by an epitaxial process without forming dislocations near gate corners. The embodiments described enable gate corners to be free of dislocation defects, preserve the device performance from degradation, and widen the process window of forming S/D regions without gate corner defects and chamber matching issues.

Abstract: An engineered epitaxial region compensates for short channel effects of a MOS device by providing a blocking layer to reduce or prevent dopant diffusion while at the same time reducing or eliminating the side effects of the blocking layer such as increased leakage current of a BJT device and/or decreased breakdown voltage of a rectifier. These side effects are reduced or eliminated by a non-conformal dopant-rich layer between the blocking layer and the substrate, which lessens the abruptness of the junction, thus lower the electric field at the junction region. Such a scheme is particularly advantageous for system on chip applications where it is desirable to manufacture MOS, BJT, and rectifier devices simultaneously with common process steps.

Abstract: A method for fabricating an integrated device is disclosed. A protective layer is formed over a gate structure when forming epitaxial (epi) features adjacent to another gate structure uncovered by the protective layer. The protective layer is thereafter removed after forming the epitaxial (epi) features. The disclosed method provides an improved method for removing the protective layer without substantial defects resulting. In an embodiment, the improved formation method is achieved by providing a protector over an oxide-base material, and then removing the protective layer using a chemical comprising hydrofluoric acid.

Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.

Abstract: The present disclosure provides a method of fabricating that includes providing a semiconductor substrate; forming a gate structure on the substrate; performing an implantation process to form a doped region in the substrate; forming spacers on sidewalls of the gate structure; performing an first etching to form a recess in the substrate, where the first etching removes a portion of the doped region; performing a second etching to expand the recess in the substrate, where the second etching includes an etchant and a catalyst that enhances an etching rate at a remaining portion of the doped region; and filling the recess with a semiconductor material.

Abstract: A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and forming a low diffusibility layer adjacent to the high diffusibility layer. After these two layers are formed, an anneal is performed to diffuse dopants from the high diffusibility layer underneath the gate stack to help form a channel region.

Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.

Abstract: A method of forming an integrated circuit includes forming a gate structure over a substrate. Portions of the substrate are removed to form recesses adjacent to the gate structure. A silicon-containing material structure is formed in each of the recesses.

Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.