Patents by Inventor Yi-Fang Pai
Yi-Fang Pai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20190355816Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.Type: ApplicationFiled: August 5, 2019Publication date: November 21, 2019Inventors: Chien-I Kuo, Shao-Fu Fu, Chia-Ling Chan, Yi-Fang Pai, Li-Li Su, Wei Hao Lu, Wei Te Chiang, Chii-Horng Li
-
Patent number: 10374038Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.Type: GrantFiled: March 15, 2018Date of Patent: August 6, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-I Kuo, Chii-Horng Li, Chia-Ling Chan, Li-Li Su, Yi-Fang Pai, Wei Te Chiang, Shao-Fu Fu, Wei Hao Lu
-
Patent number: 10340190Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure and a second fin structure over a substrate. The semiconductor device structure also includes a gate structure over the first and second fin structure. The semiconductor device structure further includes a source/drain structure over the first and second fin structure. The source/drain structure includes a first semiconductor layer over the first fin structure and a second semiconductor layer over the second fin structure. The source/drain structure also includes a third semiconductor layer covering the first and second semiconductor layers. The third semiconductor layer has a surface with [110] plane orientation.Type: GrantFiled: November 24, 2017Date of Patent: July 2, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Hao Lu, Yi-Fang Pai, Tuoh-Bin Ng, Li-Li Su, Chii-Horng Li
-
Publication number: 20190165100Abstract: The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.Type: ApplicationFiled: March 15, 2018Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-I KUO, Chii-Horng LI, Chia-Ling CHAN, Li-Li SU, Yi-Fang PAI, Wei Te CHIANG, Shao-Fu FU, Wei Hao LU
-
Publication number: 20190164835Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first fin structure and a second fin structure over a substrate. The semiconductor device structure also includes a gate structure over the first and second fin structure. The semiconductor device structure further includes a source/drain structure over the first and second fin structure. The source/drain structure includes a first semiconductor layer over the first fin structure and a second semiconductor layer over the second fin structure. The source/drain structure also includes a third semiconductor layer covering the first and second semiconductor layers. The third semiconductor layer has a surface with [110] plane orientation.Type: ApplicationFiled: November 24, 2017Publication date: May 30, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei-Hao LU, Yi-Fang PAI, Tuoh-Bin NG, Li-Li SU, Chii-Horng LI
-
Patent number: 10134896Abstract: A semiconductor substructure with an improved source/drain structure is described. The semiconductor substructure can include an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structure is disposed over or on a recess surface of a recess that extends below said upper surface. The source/drain structure includes a first epitaxial layer, having a first composition, over or on the interface surface, and a subsequent epitaxial layer, having a subsequent composition, over or on the first epitaxial layer. A dopant concentration of the subsequent composition is greater than a dopant concentration of the first composition, and a carbon concentration of the first composition ranges from 0 to 1.4 at.-%. Methods of making semiconductor substructures including improved source/drain structures are also described.Type: GrantFiled: March 1, 2013Date of Patent: November 20, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun Hsiung Tsai, Sheng-Wen Yu, Ying-Min Chou, Yi-Fang Pai
-
Patent number: 9997631Abstract: A method of forming a semiconductor device includes forming a fin on a substrate and forming a source/drain region on the fin. The method further includes forming a doped metal silicide layer on the source/drain region and forming a super-saturated doped interface between the doped metal silicide and the source/drain region. An example benefit includes reduction of contact resistance between metal silicide layers and source/drain regions.Type: GrantFiled: August 2, 2016Date of Patent: June 12, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Cheng-Yu Yang, Kai-Hsuan Lee, Sheng-Chen Wang, Sai-Hooi Yeong, Yi-Fang Pai, Yen-Ming Chen
-
Publication number: 20180033887Abstract: The integrated circuit includes a gate structure over a substrate. The integrated circuit further includes a first silicon-containing material structure in a recess adjacent to the gate structure. The first silicon-containing material structure includes a first layer having an uppermost surface below a top surface of the substrate and a bottommost surface in contact with the substrate. The first silicon-containing material structure further includes a second layer over the first layer, wherein an entirety of the second layer is co-planar with or above the top surface of the substrate. A first region of the second layer closer to the gate structure is thicker than a second region of the second layer farther from the gate structure. Thickness is measured in a direction perpendicular to the top surface of the substrate.Type: ApplicationFiled: October 6, 2017Publication date: February 1, 2018Inventors: Shih-Hsien HUANG, Yi-Fang PAI, Chien-Chang SU
-
Publication number: 20170352762Abstract: A method of forming a semiconductor device includes forming a fin on a substrate and forming a source/drain region on the fin. The method further includes forming a doped metal silicide layer on the source/drain region and forming a super-saturated doped interface between the doped metal silicide and the source/drain region. An example benefit includes reduction of contact resistance between metal silicide layers and source/drain regions.Type: ApplicationFiled: August 2, 2016Publication date: December 7, 2017Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Yu YANG, Kai-Hsuan LEE, Sheng-Chen WANG, Sai-Hooi YEONG, Yi-Fang PAI, Yen-Ming CHEN
-
Patent number: 9786780Abstract: An integrated circuit includes a gate structure over a substrate. A silicon-containing material structure is in each of recesses that are adjacent to the gate structure. The silicon-containing material structure has a first region and a second region, the second region is closer to the gate structure than the first region, and the first region is thicker than the second region.Type: GrantFiled: June 24, 2014Date of Patent: October 10, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Hsien Huang, Yi-Fang Pai, Chien-Chang Su
-
Patent number: 9666691Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.Type: GrantFiled: September 10, 2012Date of Patent: May 30, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chang Su, Tsz-Mei Kwok, Hsien-Hsin Lin, Hsueh-Chang Sung, Yi-Fang Pai, Kuan-Yu Chen
-
Patent number: 9647115Abstract: A method of forming a semiconductor structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure from the fin structure; (iii) forming a sacrificial structure surrounding the epitaxy structure; (iv) forming a dielectric layer covering the sacrificial structure; (v) forming an opening passing through the dielectric layer to partially expose the sacrificial structure; (vi) removing a portion of the sacrificial structure to expose a portion of the epitaxy structure; and (vii) forming a contact structure in contact with the exposed portion of the epitaxy structure. A semiconductor structure is disclosed herein as well.Type: GrantFiled: October 14, 2015Date of Patent: May 9, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yasutoshi Okuno, Cheng-Long Chen, Meng-Chun Chang, Sung-Li Wang, Yi-Fang Pai, Yusuke Oniki
-
Publication number: 20170110578Abstract: A method of forming a semiconductor structure includes the following operations: (i) forming a fin structure on a substrate; (ii) epitaxially growing an epitaxy structure from the fin structure; (iii) forming a sacrificial structure surrounding the epitaxy structure; (iv) forming a dielectric layer covering the sacrificial structure; (v) forming an opening passing through the dielectric layer to partially expose the sacrificial structure; (vi) removing a portion of the sacrificial structure to expose a portion of the epitaxy structure; and (vii) forming a contact structure in contact with the exposed portion of the epitaxy structure. A semiconductor structure is disclosed herein as well.Type: ApplicationFiled: October 14, 2015Publication date: April 20, 2017Inventors: Yasutoshi OKUNO, Cheng-Long CHEN, Meng-Chun CHANG, Sung-Li WANG, Yi-Fang PAI, Yusuke ONIKI
-
Patent number: 9564509Abstract: A method of fabricating an integrated circuit device includes forming a first gate structure in a first region of a substrate and a second gate structure in a second region of the substrate. The method includes forming a protective layer overlying the first and the second gate structures. The method includes removing a portion of the protective layer over the second gate structure. The method includes forming features adjacent to the second gate structure. The method further includes forming a spacer over at least a portion of the features adjacent to the second gate structure, wherein the features separate the spacer from the substrate adjacent to the second gate structure. The method includes removing the second portion of the protective layer. Removing the second portion of the protective layer includes forming a protector over the second gate structure; and performing an etching process using a chemical comprising hydrofluoric acid (HF).Type: GrantFiled: November 25, 2014Date of Patent: February 7, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Hsi Yeh, Hsien-Hsin Lin, Ying-Hsueh Chang Chien, Yi-Fang Pai, Chi-Ming Yang, Chin-Hsiang Lin
-
Patent number: 9537004Abstract: A system and method for forming semiconductor structures is disclosed. An embodiment comprises forming a high diffusibility layer adjacent to a gate stack and forming a low diffusibility layer adjacent to the high diffusibility layer. After these two layers are formed, an anneal is performed to diffuse dopants from the high diffusibility layer underneath the gate stack to help form a channel region.Type: GrantFiled: May 24, 2011Date of Patent: January 3, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chii-Ming Wu, Chien-Chang Su, Hsien-Hsin Lin, Yi-Fang Pai
-
Patent number: 9443847Abstract: An integrated circuit includes a gate structure disposed over a substrate. The integrated circuit further includes a silicon-containing material structure disposed over a recess adjacent to the gate structure. The silicon-containing material structure includes a first epitaxial layer and a second epitaxial layer. A gate corner of the gate structure is free of dislocation and a corner of the second epitaxial layer away from a surface of the substrate and next to a spacer of the gate structure includes dislocations, wherein the dislocations are away from the gate corner.Type: GrantFiled: April 1, 2015Date of Patent: September 13, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun Hsiung Tsai, Yi-Fang Pai
-
Patent number: 9412870Abstract: A device includes a substrate and a recess in the substrate. The recess has a bottom and sidewalls. The device also includes a first epitaxial layer over the bottom of the recess, and a second epitaxial layer over the first epitaxial layer and over the sidewalls of the recess, the second epitaxial layer having a different lattice constant than the substrate. The device further includes a third epitaxial layer over the second epitaxial layer and filling the recess.Type: GrantFiled: August 24, 2015Date of Patent: August 9, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: King-Yuen Wong, Chia-Yu Lu, Chien-Chang Su, Yen-Chun Lin, Yi-Fang Pai, Da-Wen Lin
-
Patent number: 9356150Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.Type: GrantFiled: August 24, 2015Date of Patent: May 31, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chang Su, Hsien-Hsin Lin, Tsz-Mei Kwok, Kuan-Yu Chen, Hsueh-Chang Sung, Yi-Fang Pai
-
Publication number: 20150364604Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.Type: ApplicationFiled: August 24, 2015Publication date: December 17, 2015Inventors: Chien-Chang Su, Hsien-Hsin Lin, Tsz-Mei Kwok, Kuan-Yu Chen, Hsueh-Chang Sung, Yi-Fang Pai
-
Publication number: 20150364602Abstract: A device includes a substrate and a recess in the substrate. The recess has a bottom and sidewalls. The device also includes a first epitaxial layer over the bottom of the recess, and a second epitaxial layer over the first epitaxial layer and over the sidewalls of the recess, the second epitaxial layer having a different lattice constant than the substrate. The device further includes a third epitaxial layer over the second epitaxial layer and filling the recess.Type: ApplicationFiled: August 24, 2015Publication date: December 17, 2015Inventors: King-Yuen Wong, Chia-Yu Lu, Chien-Chang Su, Yen-Chun Lin, Yi-Fang Pai, Da-Wen Lin