Abstract: An arithmetic unit that executes matrix multiplication operation C=A×B or matrix multiply-accumulate operation C=A×B+Cin, the arithmetic unit including the matrix A regarded as being divided into blocks Aik each being an l×1 column vector, the matrix B regarded as being divided into blocks Bkj each being a 1×m row vector, accumulating l×m outer products of the blocks Aik and the blocks Bkj in a processing tile including l×m processing elements performing element-wise multiply-accumulate operation on the matrices, and executing output-stationary systolic-array-based operation in units of the processing tile across an entirety of the arithmetic unit.

Abstract: This disclosure provides a medical and healthcare service platform that is supported by a digital data currency system and provides medical and healthcare data processing, analyzing, and predicting based on a digital human system by integrating participating parties comprising individual persons, researchers, healthcare providers, and regulatory and public sectors.

Abstract: In accordance with an embodiment, described herein is a system and method for providing query acceleration with a computing environment such as, for example, a business intelligence environment, database, data warehouse, or other type of environment that supports data analytics. A middle layer is provided as a long-term table data storage format; and one more acceleration formats, or acceleration tables, can be periodically regenerated from the middle layer, wherein a determination can be made as to whether an accelerated table exists for a dataset table, and if so, then the accelerated table is used to process the query.

Abstract: A calculator comprising an array of l×m multiply-accumulate calculators configured to perform, when L and M are both integers of 2 or more and N is an integer of 1 or more, an L×M×N matrix product calculation C=A*B or an L×M×N matrix multiply-accumulate calculation C=A*B+Cin by performing accumulations of outer products Ok of k-th column of A and k-th row of B in an array of L×M accumulators for an integer k of 0 or more and less than N, with respect to an L×N matrix A, an N×M matrix B, an L×M matrix C, and an L×M matrix Cin, wherein any one of l or m is l=L or m=M and the other one is an integer of 2?l<L or 2?m<M, and the l×m multiply-accumulate calculators perform each of the accumulations of the outer product Ok by a plurality of steps.

Abstract: In accordance with an embodiment, described herein is a system and method for providing query acceleration with a computing environment such as, for example, a business intelligence environment, database, data warehouse, or other type of environment that supports data analytics. A middle layer is provided as a long-term table data storage format; and one more acceleration formats, or acceleration tables, can be periodically regenerated from the middle layer, wherein a determination can be made as to whether an accelerated table exists for a dataset table, and if so, then the accelerated table is used to process the query.

Abstract: A processor includes a matrix scheduler, wherein the matrix scheduler includes a first latency selector disposed on an input side of each column corresponding to a producer in a matrix; and a second latency selector disposed on an output side of each row corresponding to a consumer in the matrix, and the matrix scheduler is configured to carry out wakeup operation at a latency being a sum of a latency of the first latency selector and a latency of the second latency selector on a wakeup signal path passing through the first latency selector and further passing through the second latency selector.

Abstract: An instruction processing apparatus including a processor configured to execute a process including issuing, by an instruction scheduler, instructions that can be executed; holding, by a register file, data used by the instructions; executing, by an execution unit including a plurality of stages, the instructions issued by the instruction scheduler; detecting, by a detector, early termination in which an execution result of an intermediate stage, which is before a final stage among the plurality of stages, is the same as an execution result of the execution unit; and transferring, by a bypass controller, the data output from the register file or the execution result from the execution unit, to an input of the execution unit, and in response to the detector detecting the early termination, bypassing the execution result of the intermediate stage to the input of the execution unit.

Abstract: A processor includes a queue configured to hold a memory access instruction including one or more addresses, a contracted address generator configured to generate a contracted address by contracting bits of multiple addresses in a case where the memory access instruction includes the multiple addresses, a conflict detector configured to detect a conflict between the contracted address and the address held in the queue, and an access controller configured to control processes of the memory access instruction held in the queue, based on a detection result of the conflict detector.

Abstract: Embodiments of this application disclose an application upgrade method. The method includes: obtaining upgrade information of an application, where the upgrade information includes a target operator, an operator identifier of the target operator, and an application identifier of the application; obtaining, based on a virtual address, a physical address allocated to the target operator, where the physical address is an address of storage space on a network interface card device; storing the target operator in the storage space corresponding to the physical address; and constructing a first mapping relationship based on the operator identifier, the application identifier, and the physical address, where the first mapping relationship is used as routing information of the target operator when the application is running.

Abstract: An information processing apparatus includes: a storage apparatus including a plurality of banks used as respective separate storage regions; a pipeline having a plurality of lanes in each of which processing of an instruction for reading or writing data from or to the bank is performed; a plurality of instruction processing circuits that are respectively disposed in the lanes, each access any of the banks in accordance with the instruction processed in the corresponding lane, and each execute reading or writing of data; a blocking network switch configured to selectively couple the instruction processing circuit to any one of the banks by switching a coupling path.

Abstract: An instruction processing apparatus including a processor configured to execute a process including issuing, by an instruction scheduler, instructions that can be executed; holding, by a register file, data used by the instructions; executing, by an execution unit including a plurality of stages, the instructions issued by the instruction scheduler; detecting, by a detector, early termination in which an execution result of an intermediate stage, which is before a final stage among the plurality of stages, is the same as an execution result of the execution unit; and transferring, by a bypass controller, the data output from the register file or the execution result from the execution unit, to an input of the execution unit, and in response to the detector detecting the early termination, bypassing the execution result of the intermediate stage to the input of the execution unit.

Abstract: This patent discloses a medical service platform, method, and apparatus based on a human digital twin model that comprises a a data currency valuation subsystem that provides dynamic quotes of a digital currency based on values of corresponding data in the digital human digital data currency system.

Abstract: A processor includes request issuing units issuing an access request to a storage, a data array including banks holding sub data divided from data read from the storage based on the access request, a switch to transfer the access request to one of the banks, and first and second determination units. The first determination unit determines a cache hit when a tag address included in the access address matches a tag address held therein in correspondence with an index address included in the access address. The second determination unit determines a cache hit when identification information corresponding to a first tag address included in the access address and a second tag address included in the access address, match identification information and second tag address held therein. A cache controller makes access to the data array or storage, based on a determination result of the first or second determination unit.

Abstract: This disclosure provides a medical and healthcare service platform that is supported by a digital data currency system and provides medical and healthcare data processing, analyzing, and predicting based on a digital human system by integrating participating parties comprising individual persons, researchers, healthcare providers, and regulatory and public sectors.

Abstract: A processor includes a queue configured to hold a memory access instruction including one or more addresses, a contracted address generator configured to generate a contracted address by contracting bits of multiple addresses in a case where the memory access instruction includes the multiple addresses, a conflict detector configured to detect a conflict between the contracted address and the address held in the queue, and an access controller configured to control processes of the memory access instruction held in the queue, based on a detection result of the conflict detector.

Abstract: Provided are a system for constructing a genome-wide sgRNA library and a use thereof. The system includes an input module, an sgRNA design module and an sgRNA filtering module. By constructing three modules in the system, optimizing details and processes in the modules, and adopting multiple design criteria and screening principles, the genome-wide sgRNA library is finally constructed. The system and method are concise and efficient, and the obtained library has a high quality and good activity, and is convenient for applications in gene editing researches.

Abstract: A processor includes request issuing units issuing an access request to a storage, a data array including banks holding sub data divided from data read from the storage based on the access request, a switch to transfer the access request to one of the banks, and first and second determination units. The first determination unit determines a cache hit when a tag address included in the access address matches a tag address held therein in correspondence with an index address included in the access address. The second determination unit determines a cache hit when identification information corresponding to a first tag address included in the access address and a second tag address included in the access address, match identification information and second tag address held therein. A cache controller makes access to the data array or storage, based on a determination result of the first or second determination unit.

Abstract: In accordance with an embodiment, described herein is a system and method for providing query acceleration with a computing environment such as, for example, a business intelligence environment, database, data warehouse, or other type of environment that supports data analytics. A middle layer is provided as a long-term table data storage format; and one more acceleration formats, or acceleration tables, can be periodically regenerated from the middle layer, wherein a determination can be made as to whether an accelerated table exists for a dataset table, and if so, then the accelerated table is used to process the query.

Abstract: A method and apparatus for implementing a virtual local area network. The method includes determining a global virtual local area network for transmitting a broadcast data frame in response to receiving the broadcast data frame at a first switch, encapsulating the broadcast data frame based at least in part on said determination and transmitting it to at least one second switch over the determined global virtual local area network. The broadcast data frame is received at the second switch and an identifier of the global virtual local area network is obtained according to the broadcast data frame. Based at least in part on the identifier of the global virtual local area network, it is determined that which local virtual local area network served by the second switch the de-capsulated broadcast data frame can be sent to.

Abstract: An operation processing apparatus including one or more lanes each of which processes at most one element operation of an instruction per cycle, and an element operation issuing unit that issues the element operation to the one or more lanes, wherein an entirety of the operation processing apparatus is separated into a plurality of sections by buffers including a plurality of entries, zero or more of the sections that are unable to continue processing of element operations stop the processing, and remaining sections each continue the processing of element operations by storing element operations proceeding to the downstream section into the immediately downstream buffer.