Abstract: An data supply circuit includes a buffer configured to store a plurality of data items each having a first width, a memory access unit configured to read source data stored in memory and to store the source data as one or more data items each having the first width in the buffer, and a selection control unit configured to repeat multiple times an operation of reading a data item having a second width shorter than or equal to the first width to read a plurality of data items each having the second width contiguously and sequentially from the buffer and configured to continue to read from a head end of the source data upon a read portion reaching a tail end of the source data.

Abstract: Method and apparatus for managing a translation lookaside buffer (TLB) at hardware in a virtualization enabled system. According to embodiments of the present invention, a series of operations caused by TLB miss would not need intervening from the hypervisor. On the contrary, when a TLB miss occurs, the hardware directly issues an interrupt to a virtual machine. In this way, the TLB can be efficiently managed by means of a hardware-level auxiliary translation table. Therefore, system overheads can be greatly reduced and system performance can be improved. Methods and apparatuses associated with hardware, hypervisor, and virtual machine in a virtualization enabled system are disclosed, respectively.

Abstract: A vector processing circuit includes a vector register file including a plurality of array elements, a command issuance control circuit, and a plurality of pipeline arithmetic units. Each pipeline arithmetic unit performs arithmetic processing of data stored in the array elements indicated as a source by one command in parts through a plurality of cycles and stores the result in the array elements indicated as a destination by the one command through a plurality of cycles. When data word length of a preceding command is longer than that of a subsequent command, the command issuance control circuit changes data sizes of the array elements in accordance with data word length of the command and determines whether there is register interference between the array element to be processed at a non-head cycle of the preceding command, and the array element to be processed at a head cycle of the subsequent command.

Abstract: An arithmetic processing device includes: an arithmetic unit configured to execute an arithmetic operation; and a stream engine configured to execute stream processing, wherein a data bus of the arithmetic unit and a data bus of the stream engine are tightly coupled with each other.

Abstract: A data processing apparatus includes a computing unit that performs a matrix computation between data streams whose unit data is of a matrix format; a determining unit that for each matrix obtained by the matrix computation by the computing unit, determines based on the value of each element included in the matrix, an exponent value for expressing each element included in the matrix as a floating decimal point value; a converting unit that converts the value of each element into a significand value of the element, according to the exponent value determined by the determining unit; and an output unit that correlates and outputs the exponent value and each matrix after conversion in which the value of each element in the matrix has been converted by the converting unit.

Abstract: The present disclosure provides a method, device, and system for processing a request in a multi-core system. The method comprises steps of: receiving a request for data by a filter from a requesting unit; comparing an indicator indicative of a logical partition in the request with an indicator indicative of the logical partition in a record of the filter; searching in a unit where the filter is located based on the request and returning a search result to the requesting unit if a comparison result matches; and returning a NONE response to the requesting unit from the filter if the comparison result does not match.

Abstract: A computer-implemented method, an accelerator hardware unit, and an article of manufacture for supporting virtual machine migration. The method includes: acquiring a task request from a task queue of an accelerator hardware unit; extracting identification information of a related virtual machine from the task request; determining whether the identification information of the related virtual machine matches the identification information of a virtual machine to be migrated, where the identification information of a virtual machine to be migrated is recorded in a virtual machine identification information table; and deleting the task request from the task queue if the extracted identification information matches the identification information of a virtual machine to be migrated.

Abstract: This invention relates to the Internet of Things (IOT), and discloses a method and apparatus of data filtering in the IOT, where the IOT includes a plurality of sensor devices. The method includes: inputting an application deployed rule; converting the rule into at least one sub-predicate expression having static predicates and dynamic predicates; inputting data collected by the sensor devices; matching the collected data with the static predicates and the dynamic predicates of the sub-predicate expression in sequence; and distributing matched data to the application. In this invention, a rule is divided into static and dynamic predicates, and a match is performed on static predicates before dynamic predicates, so that the speed of predicate match can be improved and fast and efficient data filtering in the IOT can be achieved.

Abstract: A matrix calculation unit may include a matrix operation unit and a converting unit. The matrix operation unit may include functions to perform a matrix operation of a first size with respect to data stored in a memory, and to perform a matrix operation of a second size with respect to the data stored in the memory, where the second size is enlarged from the first size. The converting unit may convert in at least one direction in the memory between a data array suited for the matrix operation of the first size and a data array suited for the matrix operation of the second size.

Abstract: An arithmetic processing unit that performs processing of a stream-type includes an arithmetic unit configured to operate an input operand to obtain a result of operation; and a data input and output unit configured to read the input operand out of a memory when an instruction which is issued in a case where a stream length of the input operand is shorter than a stream length of an output operand corresponding to the input operand and includes data indicating a recursive rule used when the input operand is read out, to supply the read input operand, and to store the result of the operation obtained by the arithmetic unit in the memory as the output operand, wherein the arithmetic unit 20 operates the input operand read out by the data input and output unit and outputs the result of operation to the data input and output unit.

Abstract: An uncured acoustic absorbing member (1, 31) for cavity sealing comprises a thermally inert carrier (8, 38) and a thermally expandable material (6, 40) applied to the carrier. The carrier (8, 38) contains openings (3, 33) which become covered when the thermally expandable material is expanded to seal the cavity. The acoustic absorbing members (1, 31) are particularly useful for sealing automotive cavities to provide acoustical abatement and to prevent the entry of fluids into the cavity.

Abstract: A correlation processing apparatus that obtains a correlation value between an image and a subimage, the apparatus including: N arithmetic circuits, each of the N arithmetic circuits performing an arithmetic operation on a first image pixel value of a first image pixel of the image and a second image pixel value of a second image pixel of the subimage; a rectangular pattern selection circuit selecting a rectangular pattern among a plurality of predetermined rectangular patterns, the rectangular pattern including Q elements, the smallest number of divisions is obtained if the image is divided by the rectangular pattern; a control circuit activating Q arithmetic circuits among the N arithmetic circuits and identifying Q first image pixel values and Q second image pixel values on which the arithmetic operations are performed by the Q arithmetic circuits; and an accumulator accumulating the results of the arithmetic operations performed by the Q arithmetic circuits.

Abstract: A method and an apparatus for concomitance scheduling a work thread and assistant threads associated with the work thread in a multi-threading processor system. The method includes: searching one or more assistant threads associated with the running of the work thread when preparing to run/schedule the work thread; running the one or more assistant threads that are searched; and running the work thread after all of the one or more assistant threads associated with the running of the work thread have run.

Abstract: A search device includes an accelerator and a CPU. The accelerator includes a plurality of search cores and a scheduler. The scheduler is configured to distribute target text to the search cores in units of records ordered by record sequence number, and the search cores are configured to perform automaton matching on the distributed records in a parallel fashion. The CPU is configured to construct an automaton in accordance with a search expression input thereto, and to perform logical expression evaluations in order of the record sequence number on matching results obtained on a record-by-record basis.

Abstract: A network system adopting a first IP protocol is provided. The network system includes an address allocating server and a communication terminal supporting both the first IP protocol and a second IP protocol, wherein the address allocating server dynamically allocates an address of the second IP protocol to the communication terminal.

Abstract: A cache system includes processing units operative to access a main memory device, caches coupled in one-to-one correspondence to the processing units, and a controller coupled to the caches to control data transfer between the caches and data transfer between the main memory and the caches, wherein the controller includes a memory configured to store first information and second information separately for each index, the first information indicating an order of oldness of entries in each one of the caches, and the second information indicating an order of oldness of entries for the plurality of the caches, and a logic circuit configured to select an entry to be evicted and its destination in response to the first and second information when an entry of an index corresponding to an accessed address is to be evicted from a cache corresponding to the processing unit that accesses the main memory device.

Abstract: Provided is a hardware accelerator, central processing unit, and computing device. A hardware accelerator includes a task accelerating unit configured to, in response to a request for a new task issued by a hardware thread, accelerate the processing of the new task and produce a processing result for the task; a task time prediction unit configured to predict the total waiting time of the new task for returning to a specified address associated with the hardware thread. One aspect of this disclosure makes the hardware thread aware of the time to be waited for before getting a processing result, facilitating its task planning accordingly.

Abstract: Provided is a hardware accelerator and method, central processing unit, and computing device. A hardware accelerating method includes, in response to a request for a new task issued by a hardware thread, accelerating processing of the new task and producing a processing result for the task. A predicting step predicts total waiting time of the new task for returning to a specified address associated with the hardware thread.

Abstract: A method and system for compressing and encrypting data. The method includes: receiving original data; performing a first compression of said original data to obtain a first compression result; and encrypting only a literal portion in the first compression result to obtain an encrypted first compression result. Embodiments of the present invention improve the efficiency of the process of compression +encryption to a great extent by means of encrypting only the literal portion of the compression result.

Abstract: A method and system for compressing and encrypting data. The method includes: receiving original data; performing a first compression of the original data to obtain a first compression result; and encrypting only a literal portion in the first compression result to obtain an encrypted first compression result. Various embodiments improve the efficiency of the process of compression and encryption to a great extent by encrypting only the literal portion of the compression result.