Abstract: A computer-implemented method uses a predictive time-sequence model to adapt hardware configurations at run-time for an application including multiple stages of execution. At each stage a system monitor is started at the launch of a first task in a first run to collect performance data. The system monitor is stopped at the completion of a last task in the first run, then a predictive optimal configuration is computed and applied to the remaining runs in the stage.

Abstract: The present invention provides a method and apparatus of controlling subscription requests, which can be used in a publish/subscribe engine. The method includes parsing a received subscription request into a predicate expression; determining an occurrence probability of the subscription request based on occurrence probabilities of predicates in the predicate expression; estimating a message increment to be caused by the subscription request based on a message publishing rate associated with the subscription request and on the occurrence probability of the subscription request; and controlling a quality of service of messages based on the estimated message increment.

Abstract: A signal processing device includes digital signal processing circuits. Each of the digital signal processing circuits includes: a regeneration circuit that regenerates a bit stream front an electric field information signal of an optical signal; an error correction circuit that corrects an error in the bit stream; an encoder circuit that generates an encoded bit stream from received data; and a generation circuit that generates an electric field information signal from the encoded bit stream. An electric field information signal or a bit stream is given from a regeneration circuit, an encoder circuit or a generation circuit in a first digital signal processing circuit to a second digital signal processing circuit. A regeneration circuit, an error correction circuit or a generation circuit in the second digital signal processing circuit processes the electric field information signal or the bit stream given from the first digital signal processing circuit.

Abstract: There is provided a reception device including a receiver configured to receive a wavelength-multiplexed optical signal so as to generate a wavelength-multiplexed signal, a filter configured to pass through the wavelength-multiplexed signal having a specific wavelength and an adjacent wavelength to the specific wavelength from the wavelength-multiplexed signal, and a processor configured to detect a specific signal having the specific wavelength from the wavelength-multiplexed signal having the passed through wavelengths by the filter, and detect a first supervisory control signal having the specific wavelength and a second supervisory control signal having the adjacent wavelength from the wavelength-multiplexed signal having the passed through wavelengths by the filter.

Abstract: An error correction circuit includes a first error correction circuit, a second error correction circuit and a controller. The first error correction circuit performs an error correction in a first correction scheme. The second error correction circuit performs an error correction in a second correction scheme. A correction performance of the second correction scheme is lower than a correction performance of the first correction scheme. The controller makes the first error correction circuit perform error correction of a received signal when a capacity of the received signal is smaller than or equal to a processing capacity of the first error correction circuit, and makes the first error correction circuit and the second error correction circuit perform error correction of the received signal when the capacity of the received signal is larger than the processing capacity of the first error correction circuit.

Abstract: Techniques for parsing a message comprising at least one data field are provided. One computer-implemented method comprises: determining, by an electronic device operatively coupled to a processing unit, a first model from a first category of data processing models; and determining, by the electronic device, a second model from a second category of data processing models, the second category being different from the first category. The computer-implemented method also comprises comparing, by the electronic device, performance of a first combined model of first and second models with performance of the first model; and selecting, by the electronic device, a target model for processing data from the first combined model and the first model based on the comparing.

Abstract: A method and apparatus for implementing a virtual local area network. The method includes determining a global virtual local area network for transmitting a data frame in response to receiving the data frame at a first switch, encapsulating the data frame based at least in part on said determination and transmitting it to at least one second switch over the determined global virtual local area network. The data frame is received at the second switch and an identifier of the global virtual local area network is obtained according to the data frame. Based at least in part on the identifier of the global virtual local area network, it is determined that which local virtual local area network served by the second switch the de-capsulated data frame can be sent to.

Abstract: A computer program product for performing a method comprising receiving, by a processor executing on a computing device, data to be processed from a scheduler configured to assign job data. The processor also storing the received data to be processed into a single queue, wherein the single queue is shared by the multiple virtual machines running on the physical machine, and in response to an idle virtual machine being among the multiple virtual machines, assigning, by the processor, data in the queue to the idle virtual machine to be processed by the idle virtual machine, wherein storing the received data to be processed into a single queue comprises parsing the received data to be processed and storing data to be processed, which is determined as specific to a predetermined application after the parsing, into the single queue.

Abstract: Provided is a hardware accelerator and method, central processing unit, and computing device. A hardware accelerating method includes, in response to a request for a new task issued by a hardware thread, accelerating processing of the new task and producing a processing result for the task. A predicting step predicts total waiting time of the new task for returning to a specified address associated with the hardware thread.

Abstract: Provided is a hardware accelerator, central processing unit, and computing device. A hardware accelerator includes a task accelerating unit configured to, in response to a request for a new task issued by a hardware thread, accelerate the processing of the new task and produce a processing result for the task; a task time prediction unit configured to predict the total waiting time of the new task for returning to a specified address associated with the hardware thread. One aspect of this disclosure makes the hardware thread aware of the time to be waited for before getting a processing result, facilitating its task planning accordingly.

Abstract: A signal processing device includes digital signal processing circuits. Each of the digital signal processing circuits includes: a regeneration circuit that regenerates a bit stream front an electric field information signal of an optical signal; an error correction circuit that corrects an error in the bit stream; an encoder circuit that generates an encoded bit stream from received data; and a generation circuit that generates an electric field information signal from the encoded bit stream. An electric field information signal or a bit stream is given from a regeneration circuit, an encoder circuit or a generation circuit in a first digital signal processing circuit to a second digital signal processing circuit. A regeneration circuit, an error correction circuit or a generation circuit in the second digital signal processing circuit processes the electric field information signal or the bit stream given from the first digital signal processing circuit.

Abstract: A method and apparatus for implementing a virtual local area network. The method includes determining a global virtual local area network for transmitting a data frame in response to receiving the data frame at a first switch, encapsulating the data frame based at least in part on said determination and transmitting it to at least one second switch over the determined global virtual local area network. The data frame is received at the second switch and an identifier of the global virtual local area network is obtained according to the data frame. Based at least in part on the identifier of the global virtual local area network, it is determined that which local virtual local area network served by the second switch the de-capsulated data frame can be sent to.

Abstract: An error correction circuit includes a first error correction circuit, a second error correction circuit and a controller. The first error correction circuit performs an error correction in a first correction scheme. The second error correction circuit performs an error correction in a second correction scheme. A correction performance of the second correction scheme is lower than a correction performance of the first correction scheme. The controller makes the first error correction circuit perform error correction of a received signal when a capacity of the received signal is smaller than or equal to a processing capacity of the first error correction circuit, and makes the first error correction circuit and the second error correction circuit perform error correction of the received signal when the capacity of the received signal is larger than the processing capacity of the first error correction circuit.

Abstract: A brake rotor having a substantially tubular rotor body, a first annular braking disc, a second annular braking disc, and a plurality of vanes. The first annular braking disc is directly connected to the rotor body at an inner periphery of the first braking disc. Likewise, the second annular braking disc is directly connected to the rotor body at an inner periphery of the second braking disc. The second annular braking disc is positioned a distance axially from the first braking disc, forming a space between the first braking disc and the second braking disc. The plurality of vanes is disposed within the space, and the vanes axially interconnect the first braking disc and the second braking disc.

Abstract: A method of message adaptation in the Internet of Things (IoT) includes receiving a message containing data collected by the plurality of sensors, identifying a message type, looking up a message descriptor according to the message type, looking up a message template matching the message type and outputting the message with the matched message template for content-based processing. In one embodiment, the method includes identifying the message is a text message, parsing the message according to message type and message descriptor, and creating a sequence of key-value pairs for the text message. In one embodiment the method includes determining that there is no matched or valid matched message template and parsing the message according to the message descriptor to generate and store a message template including the message type, a message item list and a message item position list and attaching the message template to the message.

Abstract: A pipeline-based processor and method. The method includes partitioning a particular pipeline into one or more base pipeline stages and a plurality of enhanced pipeline stages, each enhanced pipeline stage configured to be either a shutdown enhanced pipeline stage or an activated enhanced pipeline stage. Each enhanced pipeline stage has an enhanced stage priority level. The method also includes configuring each enhanced pipeline stage to be activated or shut down based at least on the enhanced stage priority level. The method additionally includes partitioning a particular pipeline stage into at least one base module and a plurality of enhanced modules, each enhanced pipeline stage configured to be either a shutdown enhanced pipeline stage or an activated enhanced pipeline stage. Each enhanced module has a particular priority level. The method further includes configuring each enhanced module to be activated or shut down based at least on the particular priority level.

Abstract: A data processing apparatus includes a computing unit that performs a matrix computation between data streams whose unit data is of a matrix format; a determining unit that for each matrix obtained by the matrix computation by the computing unit, determines based on the value of each element included in the matrix, an exponent value for expressing each element included in the matrix as a floating decimal point value; a converting unit that converts the value of each element into a significand value of the element, according to the exponent value determined by the determining unit; and an output unit that correlates and outputs the exponent value and each matrix after conversion in which the value of each element in the matrix has been converted by the converting unit.

Abstract: The present invention discloses a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.

Abstract: An arithmetic processing device includes: an arithmetic unit configured to execute an arithmetic operation; and a stream engine configured to execute stream processing, wherein a data bus of the arithmetic unit and a data bus of the stream engine are tightly coupled with each other.

Abstract: A system and method for patching an application running in a computing system, the method comprising: in response to that there is a need to patch a first content and the first content has been in the memory, distinguishing between a new content and an old content, the new content being the patched first content, the old content being the first content that has been in the memory; and in response to that the new content is loaded to the memory, mapping to the new content a new process that needs to apply the first content, wherein the new process comprises a process that is started after loading the new content to the memory. An apparatus for patching an application is further disclosed. With the apparatus provided, it is possible to perform dynamic patching to a virtual machine or a physical machine without stopping a running process.