Abstract: A memory device includes a plurality of semiconductor lines, such as body-tied fins, on a substrate. The lines including buried-channel regions doped for depletion mode operation. A storage structure lies on the plurality of lines, including tunnel insulating layer on the channel regions of the fins, a charge storage layer on the tunnel insulating layer, and a blocking insulating layer on the charge storage layer. A plurality of word lines overlie the storage structure and cross over the channel regions of the semiconductor lines, whereby memory cells lie at cross-points of the word lines and the semiconductor lines.

Abstract: With advanced lithographic nodes featuring a half-pitch of 30 nm or less, charge trapping NAND memory has neighboring cells sufficiently close together that fringing fields from a neighboring pass gate interferes with the threshold voltage. The interference results from fringing fields that occupy the gaps that separate the neighboring charge storage structures. The fringing electric fields are suppressed, by the insulating structures having a relative dielectric constant with respect to vacuum that is less than a relative dielectric constant of silicon oxide, from entering the neighboring charge storage structures. In some embodiments, the insulating structures suppress the fringing electric fields from entering a channel region. This suppresses the short channel effects despite the small dimensions of the devices.