Abstract: Devices and methods are described herein that obviate the need for a read assist circuit. In one example, a semiconductor device includes a source region and a drain region formed above a substrate. A buried insulator (BI) layer is formed beneath either the source region or the drain region. A first nano-sheet is formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer. The BI layer reduces current flow through the first nano-sheet.

Abstract: An integrated circuit structure is provided including a first transistor, a second transistor, a power rail, a first metal via and a plurality of metal tracks. The first transistor includes a first fin above a substrate and a source feature. The second transistor includes a second fin and a drain feature. The power rail is formed between the first fin and the second fin and below the source feature and the drain feature. The first metal via is formed over the power rail and electrically connected to source or drain feature. The metal tracks are separated from each other. Gaps between any two adjacent metal tracks are identical to each other, each of the metal tracks overlapping the power rail has a first width, each of the metal tracks not overlapping the power rail has a second width, and the first width is greater than the second width.

Abstract: A method of forming an integrated circuit structure includes placing a tap cell layout pattern on a layout level, placing a set of standard cell layout patterns adjacent to the tap cell layout pattern, and manufacturing the integrated circuit structure based on at least one of the layout patterns. The placing the first well layout pattern includes placing a first layout pattern extending in a first direction and having a first width, placing a second layout pattern adjacent to the first layout pattern, and having a second width greater than the first width, and placing a first implant layout pattern on a second layout level, extending in the first direction, overlapping the first layout pattern and having a third width greater than the first width.

Abstract: A method of forming an integrated circuit structure includes placing a tap cell layout pattern on a layout level, placing a set of standard cell layout patterns adjacent to the tap cell layout pattern, and manufacturing the integrated circuit structure based on at least one of the layout patterns. The placing the first well layout pattern includes placing a first layout pattern extending in a first direction and having a first width, placing a second layout pattern adjacent to the first layout pattern, and having a second width greater than the first width, and placing a first implant layout pattern on a second layout level, extending in the first direction, overlapping the first layout pattern and having a third width greater than the first width.

Abstract: A resonant conversion apparatus with extended hold-up time includes a resonant conversion unit, a time-extended unit, and a control unit. The resonant conversion unit includes a primary side, a transformer unit, and a secondary side. The time-extended unit includes a coil and a bridge arm assembly. When a switching frequency of the primary side is less than a critical frequency, the control unit controls the bridge arm assembly being switched on or switched off so that an output voltage of the resonant conversion apparatus is higher than a predetermined voltage within a hold-up time.

Abstract: A fin field effect transistor device structure includes a first fin structure formed on a substrate. The fin field effect transistor device structure also includes a spacer layer surrounding the first fin structure. The fin field effect transistor device structure further includes a power rail formed over the substrate besides a bottom portion of the first fin structure. The fin field effect transistor device structure further includes a first contact structure formed over the first fin structure and in contact with a portion of the power rail.

Abstract: A resonant conversion apparatus with extended hold-up time includes a resonant conversion unit, a time-extended unit, and a control unit. The resonant conversion unit includes a primary side, a transformer unit, and a secondary side. The time-extended unit includes a coil and a bridge arm assembly. When a switching frequency of the primary side is less than a critical frequency, the control unit controls the bridge arm assembly being switched on or switched off so that an output voltage of the resonant conversion apparatus is higher than a predetermined voltage within a hold-up time.

Abstract: An integrated circuit structure includes a first well, and a first and a second set of implants. The first well includes a first dopant type, a first portion extending in a first direction and having a first width, and a second portion adjacent to the first portion. The second portion extends in the first direction and has a second width greater than the first width. The first set of implants are in the first portion of the first well, and the second set of implants are in the second portion of the first well. At least one implant of the first set of implants being configured to be coupled to a first supply voltage. Each implant of the second set of implants having a second dopant type different from a first dopant type of the first set of implants.

Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.

Abstract: A method for forming a FinFET device structure includes forming a first fin structure and a second fin structure on a substrate. The method also includes depositing a first spacer layer over the first and second fin structures. The method also includes growing a power rail between the bottom portion of the first fin structure and the bottom portion of the second fin structure. The method also includes forming a second spacer layer over the sidewalls of the first spacer layer and over the top surface of the power rail. The method also includes forming a first fin isolation structure over the power rail between the first and second fin structures. The method also includes forming a first contact structure over the first fin structure and a portion of the power rail. The method also includes forming a second contact structure over the second fin structure.

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

Abstract: An integrated circuit structure is provided including a first transistor, a second transistor, a power rail, a first metal via and a plurality of metal tracks. The first transistor includes a first fin above a substrate and a source feature. The second transistor includes a second fin and a drain feature. The power rail is formed between the first fin and the second fin and below the source feature and the drain feature. The first metal via is formed over the power rail and electrically connected to source or drain feature. The metal tracks are separated from each other. Gaps between any two adjacent metal tracks are identical to each other, each of the metal tracks overlapping the power rail has a first width, each of the metal tracks not overlapping the power rail has a second width, and the first width is greater than the second width.

Abstract: A method for forming a FinFET device structure includes forming a first fin structure and a second fin structure on a substrate. The method also includes depositing a first spacer layer over the first and second fin structures. The method also includes growing a power rail between the bottom portion of the first fin structure and the bottom portion of the second fin structure. The method also includes forming a second spacer layer over the sidewalls of the first spacer layer and over the top surface of the power rail. The method also includes forming a first fin isolation structure over the power rail between the first and second fin structures. The method also includes forming a first contact structure over the first fin structure and a portion of the power rail. The method also includes forming a second contact structure over the second fin structure.

Abstract: A static random access memory (SRAM) cell includes a first p-type semiconductor fin, a first dielectric fin, a first hybrid fin, a second hybrid fin, a second dielectric fin, and a second p-type semiconductor fin disposed in this order along a first direction and oriented lengthwise along a second direction, where each of the first and the second hybrid fins has a first portion including an n-type semiconductor material and a second portion including a dielectric material. The SRAM cell further includes n-type source/drain (S/D) epitaxial features disposed over each of the first and the second p-type semiconductor fins, p-type S/D epitaxial features disposed over the first portion of each of the first and the second hybrid fins, and S/D contacts physically contacting each of the p-type S/D epitaxial features and the second portion of each of the first and the second hybrid fins.

Abstract: The present disclosure describes a method for forming metal interconnects in an integrated circuit (IC). The method includes placing a metal interconnect in a layout area, determining a location of a redundant portion of the metal interconnect, and reducing, at the location, the length of the metal interconnect by a length of the redundant portion to form one or more active portions of the metal interconnect. The length of the redundant portion is a function of a distance between adjacent gate structures of the IC. The method further includes forming the one or more active portions on an interlayer dielectric (ILD) layer of the IC and forming vias on the one or more active portions, wherein the vias are positioned about 3 nm to about 5 nm away from an end of the one or more active portions.

Abstract: The present disclosure relates to a method of chemical vapor deposition (CVD). In some embodiments, a process gas is applied into a vacuum chamber. The process gas is guided downstream the vacuum chamber through a shower head arranged under the gas import, where the process gas is redirected to be laterally unevenly distributed under the shower head. A density of the process gas increases from a center region to a peripheral region of the vacuum chamber. The process gas is then deposited onto a first substrate to form a precursor material with an uneven thickness profile as a result of uneven distribution of the process gas. The shower head has multiple control zones each having a plurality of holes disposed through the shower head.

Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device structure includes a first epitaxial structure and a second epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a first conductive via electrically connected to the first epitaxial structure through a conductive contact. The first conductive via is misaligned with the first epitaxial structure. The semiconductor device structure further includes a second conductive via electrically connected to the second epitaxial structure. The second conductive via is aligned with the second epitaxial structure.

Abstract: A method includes forming an interlayer dielectric (ILD) layer over a first epitaxial source/drain (S/D) feature and a second epitaxial S/D feature, where the first epitaxial S/D feature is disposed adjacent to the second epitaxial S/D feature, forming a dummy contact feature in the ILD layer over the first epitaxial S/D feature, removing a portion of the dummy contact feature and a portion of the ILD layer disposed above the second epitaxial S/D feature to form a first trench, removing a remaining portion of the dummy contact feature to form a second trench, and forming a metal S/D contact in the first and the second trenches.

Abstract: The present disclosure relates to a chemical vapor deposition apparatus and associated methods. In some embodiments, the CVD apparatus has a vacuum chamber and a gas import having a gas import axis through which a process gas is imported into the vacuum chamber and being arranged near an upper region of the vacuum chamber. At least one exhaust port is arranged near a bottom region of the vacuum chamber. The CVD apparatus also has a shower head arranged under the gas import having a plurality of holes formed there through. The shower head redistributes the process gas to form a precursor material with an uneven thickness that matches a remove profile of a subsequent CMP process. As a result, planarity of the formed layer after the CMP process is improved.

Abstract: The present disclosure relates to a chemical vapor deposition apparatus and associated methods. In some embodiments, the CVD apparatus has a vacuum chamber and a gas import having a gas import axis through which a process gas is imported into the vacuum chamber and being arranged near an upper region of the vacuum chamber. At least one exhaust port is arranged near a bottom region of the vacuum chamber. The CVD apparatus also has a shower head arranged under the gas import having a plurality of holes formed there through with at least two different diameters or densities. The shower head redistributes the process gas to form a precursor material with an uneven thickness that matches a remove profile of a subsequent CMP process. As a result, planarity of the formed layer after the CMP process is improved.