Abstract: The present disclosure provides an embodiment of an integrated structure that includes a first electrode of a first conductive material embedded in a first semiconductor substrate; a second electrode of a second conductive material embedded in a second semiconductor substrate; and a electrolyte disposed between the first and second electrodes. The first and second semiconductor substrates are bonded together through bonding pads such that the first and second electrodes are enclosed between the first and second semiconductor substrates. The second conductive material is different from the first conductive material.

Abstract: The present disclosure provides an embodiment of an integrated structure that includes a first electrode of a first conductive material embedded in a first semiconductor substrate; a second electrode of a second conductive material embedded in a second semiconductor substrate; and a electrolyte disposed between the first and second electrodes. The first and second semiconductor substrates are bonded together through bonding pads such that the first and second electrodes are enclosed between the first and second semiconductor substrates. The second conductive material is different from the first conductive material.

Abstract: The present disclosure relates to a chemical vapor deposition apparatus and associated methods. In some embodiments, the CVD apparatus has a vacuum chamber and a gas import having a gas import axis through which a process gas is imported into the vacuum chamber and being arranged near an upper region of the vacuum chamber. At least one exhaust port is arranged near a bottom region of the vacuum chamber. The CVD apparatus also has a shower head arranged under the gas import having a plurality of holes formed there through with at least two different diameters or densities. The shower head redistributes the process gas to form a precursor material with an uneven thickness that matches a remove profile of a subsequent CMP process. As a result, planarity of the formed layer after the CMP process is improved.

Abstract: Vertical gate all-around (VGAA) structures are described. In an embodiment, a structure including a first doped region in a substrate, a first vertical channel extending from the first doped region, a first metal-semiconductor compound region in a top surface of the first doped region, the first metal-semiconductor compound region extending along at least two sides of the first vertical channel, and a first gate electrode around the first vertical channel.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. The semiconductor device includes a semiconductor substrate, a gate structure including a gate dielectric layer and a first gate electrode layer, and a second gate electrode layer. In the method for fabricating the semiconductor device, at first, the semiconductor substrate is provided. The semiconductor substrate includes fin portions. Then, a gate dielectric layer is formed on the fin portions. Thereafter, a first gate electrode layer is formed on the gate dielectric layer. Then, the first gate electrode layer is etched. Thereafter, a second electrode layer is formed on the first gate electrode layer. Therefore, the gate electrode layer formed on the gate dielectric layer is regrown with easy control.

Abstract: In some embodiments, the present disclosure relates to a vertical transistor device, and an associated method of formation. The transistor device has a source region over a substrate and a vertical channel bar over the source region. The vertical channel bar has a bottom surface with an elongated shape. A conductive gate region is separated from sidewalls of the vertical channel bar by a gate dielectric layer. The conductive gate region has a vertical leg and a horizontal leg protruding outward from a sidewall of the vertical leg. A dielectric layer vertically extends from a plane extending along an uppermost surface of the conductive gate region to a position surrounded by the conductive gate region. A drain contact is over the vertical channel bar.

Abstract: An integrated circuit includes a substrate and a first set of functional cell units formed over the substrate. Each of the functional cell units includes a pair of functional cells that have different threshold voltages and a filler cell between the functional cells thereof. A number of the functional cell units in the first set is equal to or greater than a number of a second set of functional cell units, each of which includes a pair of functional cells that have different threshold voltages and that abut against each other. As such, a leakage current of the integrated circuit is reduced.

Abstract: A layout design of a standard cell for a set of masks includes a first gate pad layout pattern, a second gate pad layout pattern immediately adjacent to the first gate pad layout pattern, and a third gate pad layout pattern immediately adjacent to the second gate pad layout pattern. Each gate pad layout pattern has first and second sides extending along a first direction, the second side further along a second direction than the first side. A first gate pad pitch is a distance between first sides of the first and second gate pad layout patterns and has a value different from that of a second gate pad pitch that is a distance between first sides of the second and third gate pad layout patterns. Each gate pad pattern is usable for forming a gate pad surrounding a set of channel structures.

Abstract: An integrated circuit includes a substrate and a first set of functional cell units formed over the substrate. Each of the functional cell units includes a pair of functional cells that have different threshold voltages and a filler cell between the functional cells thereof. A number of the functional cell units in the first set is equal to or greater than a number of a second set of functional cell units, each of which includes a pair of functional cells that have different threshold voltages and that abut against each other. As such, a leakage current of the integrated circuit is reduced.

Abstract: An integrated circuit structure includes a first well, and a first and a second set of implants. The first well includes a first dopant type, a first portion extending in a first direction and having a first width, and a second portion adjacent to the first portion. The second portion extends in the first direction and has a second width greater than the first width. The first set of implants are in the first portion of the first well, and the second set of implants are in the second portion of the first well. At least one implant of the first set of implants being configured to be coupled to a first supply voltage. Each implant of the second set of implants having a second dopant type different from a first dopant type of the first set of implants.

Abstract: An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first semiconductor channel, a first top source/drain region over the first semiconductor channel, and a first top source/drain pad overlapping the first top source/drain region. The second vertical transistor includes a second semiconductor channel, a second top source/drain region over the second semiconductor channel, and a second top source/drain pad overlapping the second top source/drain region. A local interconnector interconnects the first top source/drain pad and the second top source/drain pad. The first top source/drain pad, the second top source/drain pad, and the local interconnector are portions of a continuous region, with no distinguishable interfaces between the first top source/drain pad, the second top source/drain pad, and the local interconnector.

Abstract: A method of forming a set of masks for manufacturing an integrated circuit includes determining a presence of a first via layout pattern and a power rail layout pattern in an original layout design. The first via layout pattern and the power rail layout pattern overlap each other. The first via layout pattern is part of a first cell layout of the original layout design. The power rail layout pattern is shared by the first cell layout and a second cell layout of the original layout design. The method further includes modifying the original layout design to become a modified layout design and forming the set of masks based on the modified layout design. The modifying the original layout design includes, if the first via layout pattern and the power rail are present in the original layout design, replacing the first via layout pattern with an enlarged via layout pattern.

Abstract: A method of fabricating a micro electro mechanical system (MEMS) structure includes providing a first substrate structure including a bonding pad structure. The bonding pad structure has at least one recess therein. A second substrate structure is provided and bonded with the bonding pad structure of the first substrate structure.

Abstract: In some embodiments, the present disclosure relates to a vertical transistor device, and an associated method of formation. The transistor device has a source region over a substrate and a vertical channel bar over the source region. The vertical channel bar has a bottom surface with an elongated shape. A conductive gate region is separated from sidewalls of the vertical channel bar by a gate dielectric layer. The conductive gate region has a vertical leg and a horizontal leg protruding outward from a sidewall of the vertical leg. A dielectric layer vertically extends from a plane extending along an uppermost surface of the conductive gate region to a position surrounded by the conductive gate region. A drain contact is over the vertical channel bar.

Abstract: A layout design of a standard cell for a set of masks includes a first gate pad layout pattern, a second gate pad layout pattern immediately adjacent to the first gate pad layout pattern, and a third gate pad layout pattern immediately adjacent to the second gate pad layout pattern. Each gate pad layout pattern has first and second sides extending along a first direction, the second side further along a second direction than the first side. A first gate pad pitch is a distance between first sides of the first and second gate pad layout patterns and has a value different from that of a second gate pad pitch that is a distance between first sides of the second and third gate pad layout patterns. Each gate pad pattern is usable for forming a gate pad surrounding a set of channel structures.

Abstract: The present disclosure relates to a vertical transistor device having rectangular vertical channel bars extending between a source region and a drain region, and an associated method of formation. In some embodiments, the vertical transistor device has a source region disposed over a semiconductor substrate. A channel region with one or more vertical channel bars is disposed over the source region. The one or more vertical channel bars have a bottom surface abutting the source region that has a rectangular shape (i.e., a shape with four sides, with adjacent sides of different length, and four right angles). A gate region is located over the source region at a position abutting the vertical channel bars, and a drain region is disposed over the gate region and the vertical channel bars. The rectangular shape of the vertical channel bars provides for a vertical device having good performance and cell area density.

Abstract: A layout design usable for manufacturing a standard cell includes a first gate pad layout pattern, a first set of channel structure layout patterns overlapping the first gate pad layout pattern, a second gate pad layout pattern, and a second set of channel structure layout patterns overlapping the second gate pad layout pattern. The first gate pad layout pattern extends along a first direction. The second gate pad layout pattern extends along a second direction. The first set of channel structure layout patterns is arranged into a first number of columns each aligned along the first direction. The second set of channel structure layout patterns is arranged into a second number of columns each aligned along the first direction. The first number and the second number are different.

Abstract: A wafer seal ring may be formed on a first and/or a second wafer. One or both of the first and/or second wafers may have one or more dies formed thereon. The wafer seal ring may be formed to surround the dies of a corresponding wafer. One or more die seal rings may be formed around the one or more dies. The wafer seal ring may be formed to a height that may be approximately equal to a height of one or more die seal rings formed on the first and/or second wafer. The wafer seal ring may be formed to provide for eutectic or fusion bonding processes. The first and second wafers may be bonded together to form a seal ring structure between the first and second wafers. The seal ring structure may provide a hermetic seal between the first and second wafers.

Abstract: An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first semiconductor channel, a first top source/drain region over the first semiconductor channel, and a first top source/drain pad overlapping the first top source/drain region. The second vertical transistor includes a second semiconductor channel, a second top source/drain region over the second semiconductor channel, and a second top source/drain pad overlapping the second top source/drain region. A local interconnector interconnects the first top source/drain pad and the second top source/drain pad. The first top source/drain pad, the second top source/drain pad, and the local interconnector are portions of a continuous region, with no distinguishable interfaces between the first top source/drain pad, the second top source/drain pad, and the local interconnector.

Abstract: An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first semiconductor channel, a first top source/drain region over the first semiconductor channel, and a first top source/drain pad overlapping the first top source/drain region. The second vertical transistor includes a second semiconductor channel, a second top source/drain region over the second semiconductor channel, and a second top source/drain pad overlapping the second top source/drain region. A local interconnector interconnects the first top source/drain pad and the second top source/drain pad. The first top source/drain pad, the second top source/drain pad, and the local interconnector are portions of a continuous region, with no distinguishable interfaces between the first top source/drain pad, the second top source/drain pad, and the local interconnector.