Patents by Inventor Yi-Hui LEE
Yi-Hui LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240319529Abstract: An electronic device includes: a first panel, a second panel, and a first adhesive member. The first panel includes a fist alignment mark. The second panel is disposed on the first panel, and includes a second alignment mark. The first adhesive member is disposed between the first panel and the second panel, and in a top view of the electronic device, a first distance is between the first adhesive member and the first alignment mark, a second distance is between the first adhesive member and the second alignment mark, the first distance is greater than zero, and the second distance is greater than zero.Type: ApplicationFiled: February 21, 2024Publication date: September 26, 2024Inventors: Yi-Hui LEE, Kuan-Chou CHEN
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Publication number: 20240282577Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate and forming a dehydrated film over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form an exposed portion and an unexposed portion of the photoresist layer. The photoresist layer is developed to remove the unexposed portion of the photoresist layer and a first portion of the dehydrated film over the unexposed portion of the photoresist layer. In an embodiment, the method includes etching the substrate by using the exposed portion of the photoresist layer as a mask.Type: ApplicationFiled: April 29, 2024Publication date: August 22, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yen-Yu CHEN, Chih-Cheng LIU, Yi-Chen KUO, Jr-Hung LI, Tze-Liang LEE, Ming-Hui WENG, Yahru CHENG
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Patent number: 12063871Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.Type: GrantFiled: August 4, 2023Date of Patent: August 13, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chiu-Jung Chiu, Ya-Sheng Feng, I-Ming Tseng, Yi-An Shih, Yu-Chun Chen, Yi-Hui Lee, Chung-Liang Chu, Hsiu-Hao Hu
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Patent number: 12053912Abstract: An extruding system includes a mixing unit configured to mix a polymeric material with a blowing agent and to form a mixture, and an injection unit coupled to the mixing unit and configured to inject the mixture. The mixing unit includes a mixing cartridge, a first mixing screw and a second mixing screw, the first and second mixing screws are disposed in the mixing cartridge. A method of extruding a mixture includes mixing a polymeric material and a blowing agent in a mixing cartridge of a mixing unit by at least one of a first and second mixing screws to form the mixture; conveying the mixture from the mixing unit to an injection unit; and discharging the mixture from the injection unit into a molding device. The mixture is sequentially in contact with the first mixing screw and the second mixing screw.Type: GrantFiled: November 17, 2020Date of Patent: August 6, 2024Assignee: KING STEEL MACHINERY CO., LTD.Inventors: Yi-Chung Lee, Liang-Hui Yeh, Ching-Hao Chen
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Patent number: 12057315Abstract: A method of forming a pattern in a photoresist layer includes forming a photoresist layer over a substrate, and reducing moisture or oxygen absorption characteristics of the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form a latent pattern, and the latent pattern is developed by applying a developer to the selectively exposed photoresist layer to form a pattern.Type: GrantFiled: May 31, 2023Date of Patent: August 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Chen Kuo, Chih-Cheng Liu, Ming-Hui Weng, Jia-Lin Wei, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
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Patent number: 12029044Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.Type: GrantFiled: March 28, 2023Date of Patent: July 2, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
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Publication number: 20240185000Abstract: In various examples, a technique for slot filling includes receiving a natural language sentence from a user and identifying a first mention span included in the natural language sentence. The technique also includes determining, using a first machine learning model, that the first mention span is associated with a first slot class included in a set of slot classes based on a set of slot class descriptions corresponding to the set of slot classes.Type: ApplicationFiled: December 2, 2022Publication date: June 6, 2024Inventors: Shubhadeep DAS, Yi-Hui LEE, Oluwatobi OLABIYI, Zhilin WANG
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Patent number: 11957064Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.Type: GrantFiled: October 18, 2022Date of Patent: April 9, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Patent number: 11927793Abstract: A double-sided display device includes a first panel, a second panel, a light guide plate and a light source. The second panel is arranged opposite to the first panel. The light guide plate is arranged between the first panel and the second panel, and includes a main body portion including a first surface and a second surface, a first pattern arranged on the first surface, and a second pattern arranged on the second surface. The light source is arranged adjacent to the light guide plate. The first pattern is different from the second pattern.Type: GrantFiled: February 28, 2023Date of Patent: March 12, 2024Assignee: INNOLUX CORPORATIONInventors: Yi-Hui Lee, Kuan-Chou Chen, Yung-Chih Cheng
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Publication number: 20240081157Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.Type: ApplicationFiled: November 6, 2023Publication date: March 7, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Publication number: 20240074328Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.Type: ApplicationFiled: November 6, 2023Publication date: February 29, 2024Applicant: United Microelectronics Corp.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Publication number: 20240032439Abstract: A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.Type: ApplicationFiled: September 27, 2023Publication date: January 25, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, JUN XIE
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Publication number: 20240027811Abstract: A display device, including a first display panel, a second display panel, and a first optical structure layer, is provided. The first display panel has a first display surface emitting light toward a first direction. The second display panel has a second display surface emitting light toward a second direction, wherein the first direction is different from the second direction. The first optical structure layer is disposed on the first display panel, wherein a glossiness of the first optical structure layer is between 4 GU and 35 GU, and a reflectivity of specular component included (SCI) of the first optical structure layer is between 3% and 6%. The display device provided by the disclosure can reduce the influence of ambient light from the outside on a displayed image.Type: ApplicationFiled: June 8, 2023Publication date: January 25, 2024Applicant: Innolux CorporationInventors: Yu-Chun Hsu, Wei-Ming Chu, Yi-Hui Lee, Yung-Chih Cheng, Kuan-Chou Chen, Sheng-Nan Fan
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Patent number: 11849648Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.Type: GrantFiled: June 8, 2021Date of Patent: December 19, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Yi-Wei Tseng, Chin-Yang Hsieh, Jing-Yin Jhang, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Yu-Ping Wang
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Publication number: 20230380296Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.Type: ApplicationFiled: August 4, 2023Publication date: November 23, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chiu-Jung Chiu, Ya-Sheng Feng, I-Ming Tseng, Yi-An Shih, Yu-Chun Chen, Yi-Hui Lee, Chung-Liang Chu, Hsiu-Hao Hu
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Patent number: 11812669Abstract: A magnetoresistive random access memory (MRAM), including a bottom electrode layer on a substrate, a magnetic tunnel junction stack on the bottom electrode layer, a top electrode layer on the magnetic tunnel junction stack, and a hard mask layer on said top electrode layer, wherein the material of top electrode layer is titanium nitride, a material of said hard mask layer is tantalum or tantalum nitride, and the percentage of nitrogen in the titanium nitride gradually decreases from the top surface of top electrode layer to the bottom surface of top electrode layer.Type: GrantFiled: June 9, 2022Date of Patent: November 7, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, Jing-Yin Jhang, I-Ming Tseng, Yu-Ping Wang, Chien-Ting Lin, Kun-Chen Ho, Yi-Syun Chou, Chang-Min Li, Yi-Wei Tseng, Yu-Tsung Lai, Jun Xie
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Publication number: 20230314693Abstract: A double-sided display device includes a first panel, a second panel, a light guide plate and a light source. The second panel is arranged opposite to the first panel. The light guide plate is arranged between the first panel and the second panel, and includes a main body portion including a first surface and a second surface, a first pattern arranged on the first surface, and a second pattern arranged on the second surface. The light source is arranged adjacent to the light guide plate. The first pattern is different from the second pattern.Type: ApplicationFiled: February 28, 2023Publication date: October 5, 2023Inventors: Yi-Hui LEE, Kuan-Chou CHEN, Yung-Chih CHENG
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Patent number: 11765983Abstract: A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a trench in the IMD layer, forming a synthetic antiferromagnetic (SAF) layer in the trench, forming a metal layer on the SAF layer, planarizing the metal layer and the SAF layer to form a metal interconnection, and forming a magnetic tunneling junction (MTJ) on the metal interconnection.Type: GrantFiled: October 24, 2022Date of Patent: September 19, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chiu-Jung Chiu, Ya-Sheng Feng, I-Ming Tseng, Yi-An Shih, Yu-Chun Chen, Yi-Hui Lee, Chung-Liang Chu, Hsiu-Hao Hu
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Publication number: 20230238043Abstract: A semiconductor structure includes a substrate having a memory device region and a logic device region, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer on the memory device region, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and completely filling the spaces between the memory stack structures, and a first interconnecting structure formed in the second dielectric layer on the logic device region. A top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures.Type: ApplicationFiled: March 28, 2023Publication date: July 27, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Yu-Ping Wang, Chen-Yi Weng, Chin-Yang Hsieh, Yi-Hui Lee, Ying-Cheng Liu, Yi-An Shih, I-Ming Tseng, Jing-Yin Jhang, Chien-Ting Lin
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Publication number: 20230220350Abstract: Accordingly. the present disclosure provides a population of genetically engineered mesenchymal stem cells (MSCs), comprising an expression vector comprising an Akt or HGF gene and a PD-L1 gene. Also provided is a method for synergistically increasing survival status and immunomodulatory ability of an MSC or enhancing proliferation of an MSC, comprising transfecting an MSC with an Akt or HGF gene and a PD-L1 gene and a method for preventing, ameliorating and/or treating an ischemia condition, enhancing neuroregeneration or reducing neuronal death, comprising administering an effective amount of a population of genetically engineered MSCs of the present disclosure to a subject in need thereof.Type: ApplicationFiled: September 27, 2020Publication date: July 13, 2023Inventors: Woei-Cherng SHYU, Chien-Lin CHEN, Yi-Hui LEE, Long-Bin JENG, Chang-Hai TSAI