Patents by Inventor Yi-Hui LEE

Yi-Hui LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9530778
    Abstract: Semiconductor devices having metal gate include a substrate, a first nFET device formed thereon, and a second nFET device formed thereon. The first nFET device includes a first n-metal gate, and the first n-metal gate includes a third bottom barrier metal layer and an n type work function metal layer. The n type work function metal layer directly contacts the third bottom barrier layer. The second nFET device includes a second n-metal gate and the second n-metal gate includes a second bottom barrier metal layer, the n type work function metal layer, and a third p type work function metal layer sandwiched between the second bottom barrier metal layer and the n type work function metal layer. The third p type work function metal layer of the second nFET device and the third bottom barrier metal layer of the first nFET device include a same material.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chao-Hung Lin, Chih-Kai Hsu, Li-Wei Feng, Shih-Hung Tsai, Chien-Ting Lin, Jyh-Shyang Jenq, Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen
  • Publication number: 20160351575
    Abstract: The present invention provides a semiconductor structure, including a substrate, a plurality of fin structures, a plurality of gate structures, a dielectric layer and a plurality of contact plugs. The substrate has a memory region. The fin structures are disposed on the substrate in the memory region, each of which stretches along a first direction. The gate structures are disposed on the fin structures, each of which stretches along a second direction. The dielectric layer is disposed on the gate structures and the fin structures. The contact plugs are disposed in the dielectric layer and electrically connected to a source/drain region in the fin structure. From a top view, the contact plug has a trapezoid shape or a pentagon shape. The present invention further provides a method for forming the same.
    Type: Application
    Filed: July 7, 2015
    Publication date: December 1, 2016
    Inventors: Ching-Wen Hung, Wei-Cyuan Lo, Ming-Jui Chen, Chia-Lin Lu, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Yi-Kuan Wu, Chih-Sen Huang, Yi-Wei Chen, Tan-Ya Yin, Chia-Wei Huang, Shu-Ru Wang, Yung-Feng Cheng
  • Patent number: 9466521
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first metal gate on the substrate; a first hard mask on the first metal gate; an interlayer dielectric (ILD) layer on top of and around the first metal gate; and a patterned metal layer embedded in the ILD layer, in which the top surface of the patterned metal layer is lower than the top surface of the first hard mask.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: October 11, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Yi-Hui Lee, Yi-Wei Chen
  • Patent number: 9455227
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure on the substrate; forming a first contact plug adjacent to the first gate structure; and performing a replacement metal gate (RMG) process to transform the first gate structure into metal gate.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: September 27, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang, Chun-Hsien Lin
  • Publication number: 20160240540
    Abstract: A semiconductor structure is provided, including a substrate, a plurality of first semiconductor devices, a plurality of second semiconductor devices, and a plurality of dummy slot contacts. The substrate has a device region, wherein the device region includes a first functional region and a second functional region, and a dummy region is disposed therebetween. The first semiconductor devices and a plurality of first slot contacts are disposed in the first functional region. The second semiconductor devices and a plurality of second slot contacts are disposed in the second functional region. The dummy slot contacts are disposed in the dummy region.
    Type: Application
    Filed: February 12, 2015
    Publication date: August 18, 2016
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Chih-Sen Huang, Yi-Wei Chen
  • Patent number: 9412745
    Abstract: A semiconductor structure is provided, including a substrate, a plurality of first semiconductor devices, a plurality of second semiconductor devices, and a plurality of dummy slot contacts. The substrate has a device region, wherein the device region includes a first functional region and a second functional region, and a dummy region is disposed therebetween. The first semiconductor devices and a plurality of first slot contacts are disposed in the first functional region. The second semiconductor devices and a plurality of second slot contacts are disposed in the second functional region. The dummy slot contacts are disposed in the dummy region.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: August 9, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Chih-Sen Huang, Yi-Wei Chen
  • Publication number: 20160225662
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a dielectric layer on the ILD layer and the gate structure; forming an opening in the dielectric layer and the ILD layer; forming an organic dielectric layer (ODL) on the dielectric layer and in the opening; removing part of the ODL; removing part of the dielectric layer for extending the opening; removing the remaining ODL; and forming a contact plug in the opening.
    Type: Application
    Filed: February 2, 2015
    Publication date: August 4, 2016
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Feng-Yi Chang, Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Yi-Kuan Wu, Ying-Cheng Liu, Chih-Sen Huang, Yi-Wei Chen
  • Publication number: 20160204053
    Abstract: The invention provides a semiconductor package. The semiconductor package includes a lead frame including a die peddle. A supporting bar connects to the die peddle, extending in an outward direction from the die peddle. At least two power leads are separated from the die peddle and the supporting bar, having first terminals close to the die peddle and second terminals extending outward from the die peddle. A power bar connects to the at least two power leads, having a supporting portion. A molding material encapsulates the lead frame leaving the supporting portion exposed.
    Type: Application
    Filed: September 22, 2015
    Publication date: July 14, 2016
    Inventors: Tung-Hsien HSIEH, Yi-Hui LEE
  • Patent number: 9324610
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.
    Type: Grant
    Filed: August 10, 2014
    Date of Patent: April 26, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Ching-Ling Lin, Yi-Hui Lee, Chih-Sen Huang, Yi-Wei Chen, Chun-Hsien Lin
  • Publication number: 20160104612
    Abstract: The method for cleaning a contact hole and forming a contact plug therein is provided. The method includes steps of: providing a silicon substrate; forming a contact hole in the silicon substrate; performing a pre-cleaning process to clean the contact hole; and forming a contact plug in the contact hole. The pre-cleaning process includes steps of: performing an oxide dry etching process; performing a first thermal annealing process with a temperature which is equal to or greater than 300° C.; performing a degassing process with a temperature which is equal to or greater than 300° C.; and performing an Ar-plasma etching process.
    Type: Application
    Filed: October 9, 2014
    Publication date: April 14, 2016
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: YI-HUI LEE, TSUNG-HUNG CHANG, CHING-WEN HUNG, JIA-RONG WU, CHING-LING LIN, CHIH-SEN HUANG, YI-WEI CHEN, CHIA-CHANG HSU, SHU-MIN HUANG, HSIN-FU HUANG
  • Publication number: 20160104646
    Abstract: A manufacturing method for forming a semiconductor device includes: first, a substrate is provided, a fin structure is formed on the substrate, and a plurality of gate structures are formed on the fin structure, next, a hard mask layer and a first photoresist layer are formed on the fin structure, an first etching process is then performed on the first photoresist layer, afterwards, a plurality of patterned photoresist layers are formed on the remaining first photoresist layer and the remaining hard mask layer, where each patterned photoresist layer is disposed right above each gate structure, and the width of each patterned photoresist is larger than the width of each gate structure, and the patterned photoresist layer is used as a hard mask to perform an second etching process to form a plurality of second trenches.
    Type: Application
    Filed: October 14, 2014
    Publication date: April 14, 2016
    Inventors: Ching-Wen Hung, Tsung-Hung Chang, Jia-Rong Wu, Ching-Ling Lin, Yi-Hui Lee, Chih-Sen Huang, Yi-Wei Chen
  • Patent number: 9312121
    Abstract: The method for cleaning a contact hole and forming a contact plug therein is provided. The method includes steps of: providing a silicon substrate; forming a contact hole in the silicon substrate; performing a pre-cleaning process to clean the contact hole; and forming a contact plug in the contact hole. The pre-cleaning process includes steps of: performing an oxide dry etching process; performing a first thermal annealing process with a temperature which is equal to or greater than 300° C.; performing a degassing process with a temperature which is equal to or greater than 300° C.; and performing an Ar-plasma etching process.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: April 12, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Yi-Hui Lee, Tsung-Hung Chang, Ching-Wen Hung, Jia-Rong Wu, Ching-Ling Lin, Chih-Sen Huang, Yi-Wei Chen, Chia-Chang Hsu, Shu-Min Huang, Hsin-Fu Huang
  • Publication number: 20160071800
    Abstract: A semiconductor structure including a dielectric layer, a titanium layer, a titanium nitride layer and a metal is provided. The dielectric layer is disposed on a substrate, wherein the dielectric layer has a via. The titanium layer covers the via, wherein the titanium layer has tensile stress lower than 1500 Mpa. The titanium nitride layer conformally covers the titanium layer. The metal fills the via. The present invention also provides a semiconductor process for forming said semiconductor structure. The semiconductor process includes the following steps. A dielectric layer is formed on a substrate, wherein the dielectric has a via. A titanium layer conformally covers the via, wherein the titanium layer has compressive stress lower than 500 Mpa. A titanium nitride layer is formed to conformally cover the titanium layer. A metal fills the via.
    Type: Application
    Filed: October 14, 2014
    Publication date: March 10, 2016
    Inventors: Ching-Wen Hung, Tsung-Hung Chang, Yi-Hui Lee, Chih-Sen Huang, Yi-Wei Chen, Chia Chang Hsu, Hsin-Fu Huang, Chun-Yuan Wu, Shih-Fang Tzou
  • Publication number: 20160064327
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a substrate; a first metal gate on the substrate; a first hard mask on the first metal gate; an interlayer dielectric (ILD) layer on top of and around the first metal gate; and a patterned metal layer embedded in the ILD layer, in which the top surface of the patterned metal layer is lower than the top surface of the first hard mask.
    Type: Application
    Filed: September 24, 2014
    Publication date: March 3, 2016
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Yi-Hui Lee, Yi-Wei Chen
  • Patent number: 9263392
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a metal gate thereon and an interlayer dielectric (ILD) layer around the metal gate; removing part of the metal gate to form a recess; and depositing a mask layer in the recess and on the ILD layer while forming a void in the recess.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: February 16, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Ling Lin, Chih-Sen Huang, Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Yi-Hui Lee, Yi-Wei Chen
  • Publication number: 20160013104
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one metal gate thereon, a source/drain region adjacent to two sides of the at least one metal gate, and an interlayer dielectric (ILD) layer around the at least one metal gate; forming a plurality of contact holes in the ILD layer to expose the source/drain region; forming a first metal layer in the contact holes; performing a first thermal treatment process; and performing a second thermal treatment process.
    Type: Application
    Filed: August 10, 2014
    Publication date: January 14, 2016
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Tsung-Hung Chang, Ching-Ling Lin, Yi-Hui Lee, Chih-Sen Huang, Yi-Wei Chen, Chun-Hsien Lin
  • Publication number: 20130192521
    Abstract: The disclosure provides a compensating design method for a shadow mask including: providing a first shadow mask having a first opening pattern and a first material pattern; disposing the first shadow mask on a substrate having a predetermined depositing film area with first and second sides; performing a deposition process by using the first shadow mask as a mask to form a film on an actual depositing film area, wherein the distance between the first and the third sides is a first bias, and the distance between the second and the fourth sides is a second bias, and a single side gray zone of the actual depositing film area relative to the predetermined depositing film area is substantially half of the sum of the first and the second biases; and designing a second shadow mask according to the single side gray zone.
    Type: Application
    Filed: January 30, 2013
    Publication date: August 1, 2013
    Applicant: INNOLUX CORPORATION
    Inventors: Chi-Pao CHU, I-Tang JIANG, Sz-Hsiao CHEN, Kuan-Yi YANG, Kuan-Chou CHEN, Yi-Hui LEE, Chin-Kuei WEN