Patents by Inventor Yi Hung

Yi Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955417
    Abstract: An electronic device includes a substrate, an upper conductive layer, and a lower conductive layer. The substrate has a plurality of inner vias and has an upper surface and a lower surface. The upper conductive layer includes an upper ground trace and an upper signal pad disposed on the upper surface. The upper ground trace is electrically connected to the ground vias and has an upper hollow portion exposing a part of the upper surface. The upper signal pad is disposed on the part of the upper surface exposed by the upper hollow portion and electrically connected to the signal via. The lower conductive layer includes a lower ground trace and a lower signal pad disposed on the lower surface. The lower conductive trace is electrically connected to the ground vias and has a lower hollow portion exposing a part of the lower surface. The lower signal pad is disposed on the part of the lower surface exposed by the lower hollow portion and electrically connected to the signal via.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: April 9, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tsung-Yi Hung, Shih-Hsien Wu
  • Publication number: 20240113183
    Abstract: Methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (AlW); and a fill material over the first work function tuning layer.
    Type: Application
    Filed: November 30, 2023
    Publication date: April 4, 2024
    Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Weng Chang, Chi On Chui
  • Publication number: 20240113695
    Abstract: A modulation device including a plurality of electronic elements, at least one first signal line and a first driving circuit is provided. The at least one first signal line is respectively electrically connected to at least one of the electronic elements. The first driving circuit is electrically connected to the at least one first signal line. The first driving circuit provides a first signal to at least one of the at least one first signal line. The first signal includes a first pulse. The first pulse includes a first section and a second section closely adjacent to the first section.
    Type: Application
    Filed: August 30, 2023
    Publication date: April 4, 2024
    Applicant: Innolux Corporation
    Inventors: Yi-Hung Lin, Kung-Chen Kuo, Yu-Chia Huang, Nai-Fang Hsu
  • Publication number: 20240103577
    Abstract: In one example, an electronic device may include a main body, and a back cover having an opening. The back cover may include an inner surface, and a hook protruding from the inner surface. The hook may be engageable with a receiving portion of the main body to slidably couple the back cover to the main body. Further, electronic device may include a component housing connected to the main body through the opening in the back cover to fixedly couple the back cover to the main body.
    Type: Application
    Filed: November 5, 2019
    Publication date: March 28, 2024
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Cheng-Yi Yang, Szu Tao Tong, Hai-Lung Hung
  • Publication number: 20240105817
    Abstract: A semiconductor device includes a semiconductor channel. The semiconductor device includes a metal gate structure disposed over the semiconductor channel. The semiconductor device includes a gate electrode having a bottom surface contacting an upper surface of the metal gate structure. The gate electrode has its side portions extending from its top surface toward the semiconductor fin with a first depth and a central portion extending from its top surface toward the semiconductor fin with a second depth, the first depth being substantially greater than the second depth.
    Type: Application
    Filed: February 16, 2023
    Publication date: March 28, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-He Tsai, Yi-Hung Chang, Lung Chen, Long-Jie Hong
  • Patent number: 11943935
    Abstract: A layout pattern of a magnetoresistive random access memory (MRAM) includes a substrate having a first cell region, a second cell region, a third cell region, and a fourth cell region and a diffusion region on the substrate extending through the first cell region, the second cell region, the third cell region, and the fourth cell region. Preferably, the diffusion region includes a H-shape according to a top view.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: March 26, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Yen Tseng, Shu-Ru Wang, Yu-Tse Kuo, Chang-Hung Chen, Yi-Ting Wu, Shu-Wei Yeh, Ya-Lan Chiou, Chun-Hsien Huang
  • Publication number: 20240094498
    Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable portion used for connecting an optical element, a fixed portion, and a driving assembly used for driving the movable portion to move relative to the fixed portion. The movable portion is movable relative to the fixed portion.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 21, 2024
    Inventors: Po-Xiang ZHUANG, Chen-Hung CHAO, Wei-Jhe SHEN, Shou-Jen LIU, Kun-Shih LIN, Yi-Ho CHEN
  • Publication number: 20240095933
    Abstract: An image processing method for a video processor, for generating an extrapolated frame according to a previous frame and a current frame, includes steps of: projecting a plurality of motion vectors (MVs) to the extrapolated frame subsequent to the current frame; determining whether a block of the extrapolated frame is projected by at least two of the MVs; selecting at least two candidate MVs from the MVs projected to the block when the block is projected by at least two of the MVs; calculating a blended MV which is a mixture of the at least two candidate MVs, and projecting the blended MV to the previous frame; obtaining a reference MV corresponding to position of the previous frame projected by the blended MV; and comparing the reference MV with the at least two candidate MVs, to select a final MV for the block from the at least two candidate MVs.
    Type: Application
    Filed: September 21, 2022
    Publication date: March 21, 2024
    Applicant: NOVATEK Microelectronics Corp.
    Inventors: Yi-Hung Huang, Hsiao-En Chang
  • Publication number: 20240096835
    Abstract: A method of manufacturing an electronic package is provided, in which an electronic element is disposed on a carrier structure; a heat dissipation body of a heat dissipation structure is disposed on the electronic element via a heat dissipation material; the heat dissipation material is cured; supporting legs of the heat dissipation structure are fixed on the carrier structure via a bonding layer; and the bonding layer is cured. Therefore, the heat dissipation structure can be effectively fixed to the heat dissipation material and the bonding layer by completing the arrangements of the heat dissipation material and the bonding layer in stages.
    Type: Application
    Filed: November 16, 2022
    Publication date: March 21, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Pin-Jing SU, Liang-Yi HUNG, Yu-Po WANG
  • Publication number: 20240096998
    Abstract: The present disclosure describes a method for forming metallization layers that include a ruthenium metal liner and a cobalt metal fill. The method includes depositing a first dielectric on a substrate having a gate structure and source/drain (S/D) structures, forming an opening in the first dielectric to expose the S/D structures, and depositing a ruthenium metal on bottom and sidewall surfaces of the opening. The method further includes depositing a cobalt metal on the ruthenium metal to fill the opening, reflowing the cobalt metal, and planarizing the cobalt and ruthenium metals to form S/D conductive structures with a top surface coplanar with a top surface of the first dielectric.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chij-chien CHI, Yi-Ying LIU, Chia-Hung CHU, Hsu-Kai CHANG, Cheng-Wei CHANG, Chein-Shun LIAO, Keng-chu LIN, KAi-Ting HUANG
  • Publication number: 20240097051
    Abstract: A Schottky diode includes a substrate, a first drift region in the substrate, a second drift region in the substrate, a first dielectric layer disposed over the substrate, a first doped region in the first drift region, a second doped region in the second drift region, a third doped region in the first drift region, and a metal field plate disposed over the first dielectric layer. The first drift region and the first doped region include a first conductivity type. The second drift region, the second doped region and third doped region include a second conductivity type complementary to the first conductivity type. The first dielectric layer overlaps a portion of the first drift region and a portion of the second drift region. The second doped region is separated from the first doped region.
    Type: Application
    Filed: January 16, 2023
    Publication date: March 21, 2024
    Inventors: GUAN-YI LI, CHIA-CHENG HO, CHAN-YU HUNG, FEI-YUN CHEN
  • Patent number: 11935754
    Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a high-k gate dielectric around the first nanostructure and the second nanostructure, the high-k gate dielectric having a first portion on a top surface of the first nano structure and a second portion on a bottom surface of the second nanostructure; and a gate electrode over the high-k gate dielectric. The gate electrode comprises: a first work function metal around the first nanostructure and the second nanostructure, the first work function metal filling a region between the first portion of the high-k gate dielectric and the second portion of the high-k gate dielectric; and a tungsten layer over the first work function metal, the tungsten layer being free of fluorine.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Chi On Chui
  • Patent number: 11933309
    Abstract: A method for controlling a fan in a fan start-up stage including a first time period and a second time period comprises the following steps of: during the first time period, continuously providing a first driving signal to drive the fan; and during the second time period, continuously providing a second driving signal to drive the fan; wherein, the signal value of the first driving signal gradually decreases until being equal to the signal value of the second driving signal. Wherein the signal value of the first driving signal non-linearly decreases, the signal value of the second driving signal is an unchanged value. Wherein, the first time period and the second time period are adjusted for a different fan but the sum of the first time period and the second time period is always the same. A fan is also disclosed.
    Type: Grant
    Filed: July 22, 2022
    Date of Patent: March 19, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yi-Fan Lin, Chung-Hung Tang, Cheng-Chieh Liu, Chun-Lung Chiu
  • Publication number: 20240081525
    Abstract: A multifunctional table includes a table body, a carrier member, and a holder. The table body includes a board and a support member connected to each other. The board has a table top and a groove. The carrier member is connected to the table body and includes a first slideway. The holder includes a slidable attaching portion and a holding portion connected to each other. The holding portion includes a first holding surface. The first holding surface corresponds to the groove when the slidable attaching portion is slidably attached to the first slideway in a first attached state. A holder includes a slidable attaching portion and a holding portion connected to each other. The holding portion includes a first holding surface and a second holding surface opposite to each other. The first holding surface and the second holding surface are asymmetrical about a central x axis of the holder.
    Type: Application
    Filed: September 8, 2022
    Publication date: March 14, 2024
    Applicant: Nonet Inc.
    Inventors: Wilco Wijnand Soetman, Beico Chiu, Wei-Hsiang Hung, Chun-Yi Lu, Xiang-Yi Zhan
  • Publication number: 20240085667
    Abstract: A photolithography projection lens, having a plurality of lens elements and a light diaphragm arranged among them, arranged along an optical axis, and comprising an object side and an image side respectively arranged at the front and rear ends of the plurality of lens elements; wherein: the diopters of the two lenses respectively near the object side and the image side must be positive; each of the lens elements is a single lens without cement; the angle between the chief rays at different image height positions and the optical axis is <1 degree, and the angle between the chief rays at different object height positions and the optical axis is <1 degree; and under the projection of 350˜450 nm wavelength light, it provide the imaging effect of precise magnification.
    Type: Application
    Filed: September 14, 2022
    Publication date: March 14, 2024
    Inventors: SHENG CHE WU, YU HUNG CHOU, YI HUA LIN, YUAN HUNG SU
  • Publication number: 20240084447
    Abstract: A sealing article includes a body and a coating layer disposed on at least one surface of the body. The body comprises a polymeric elastomer such as perfluoroelastomer or fluoroelastomer. The coating layer comprises at least one metal. The sealing article may be a seal, a gasket, an O-ring, a T-ring or any other suitable product. The sealing article is resistant to ultra-violet (UV) light and plasma, and may be used for sealing a semiconductor processing chamber.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Peng-Cheng Hong, Jun-Liang Pu, W.L. Hsu, Chung-Hao Kao, Chia-Chun Hung, Cheng-Yi Wu, Chin-Szu Lee
  • Publication number: 20240088026
    Abstract: A semiconductor device according to embodiments of the present disclosure includes a first die including a first bonding layer and a second die including a second hybrid bonding layer. The first bonding layer includes a first dielectric layer and a first metal coil embedded in the first dielectric layer. The second bonding layer includes a second dielectric layer and a second metal coil embedded in the second dielectric layer. The second hybrid bonding layer is bonded to the first hybrid bonding layer such that the first dielectric layer is bonded to the second dielectric layer and the first metal coil is bonded to the second metal coil.
    Type: Application
    Filed: January 17, 2023
    Publication date: March 14, 2024
    Inventors: Yi Ching Ong, Wei-Cheng Wu, Chien Hung Liu, Harry-Haklay Chuang, Yu-Sheng Chen, Yu-Jen Wang, Kuo-Ching Huang
  • Publication number: 20240085726
    Abstract: A contact lens and a method of manufacturing the same are provided. The contact lens includes a contact lens body and a blue light blocking material. The blue light blocking material covers the contact lens body. The blue light blocking material includes a plurality of metal particles dispersed on the contact lens body. The contact lens has good blue light blocking efficacy and surface properties.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Hsien-Ting CHIU, Yi-Hung LIN, Ying-Jhen HUANG
  • Publication number: 20240088650
    Abstract: In some aspects of the present disclosure, an electrostatic discharge (ESD) protection circuit is disclosed. In some aspects, the ESD protection circuit includes a first transistor coupled to a pad, a second transistor coupled between the first transistor and ground, a stack of transistors coupled to the first transistor, and an ESD clamp coupled between the stack of transistors and the ground.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Li-Wei Chu, Tao Yi Hung, Chia-Hui Chen, Wun-Jie Lin, Jam-Wem Lee
  • Patent number: D1018907
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: March 19, 2024
    Assignee: CHENG UEI PRECISION INDUSTRY CO., LTD.
    Inventors: Yun-Chien Lee, Yi-Ching Hsu, Pei-Yi Lin, Yu-Hung Su, Sheng-Yuan Huang, Chun-Fu Lin