Abstract: A manufacturing method of a package structure including the following steps is provided. A carrier is provided. An anti-warpage structure is formed on the carrier. And a redistribution layer is formed on the carrier. In the normal direction of the carrier, a warpage trend of the anti-warpage structure is opposite to a warpage trend of the redistribution layer.

Abstract: A semiconductor device includes a device wafer including a first side and a second side opposite to each other, and a carrier wafer disposed over the first side of the device wafer. The carrier wafer includes an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a first diode and a second diode. The first diode is operatively coupled to a first power rail, and the second diode is operatively coupled to a second power rail at least through the device wafer.

Abstract: An apparatus is disclosed for robust transistor circuitry. In example implementations, an apparatus includes a current mirror and fault handler circuitry that is coupled to the current mirror. The current mirror includes a core transistor having a control terminal, a first transistor, and a second transistor. The first transistor has a control terminal that is coupled to the control terminal of the core transistor. The second transistor has a control terminal that is coupled to the control terminal of the core transistor. The fault handler circuitry is configured to select the first transistor or the second transistor to provide a mirrored current of the current mirror.

Abstract: The teaching equipment of an electromechanical system provided by the present invention is used to connect an emergency stop loop of electromechanical equipment, including a multi-stage key switch, an enabling switch and a safety control device. The multi-stage key switch is used to switch between a first mode and a second mode. The multi-stage key switch generates a switching signal during switching. The enabling switch is connected to the emergency stop loop. The safety control device is used to receive the switching signal. The safety control device includes a transient emergency stop circuit and a disconnection loop time. The safety control device triggers the emergency stop loop to enter the emergency stop state according to the switching signal. The emergency stop state includes that the transient emergency stop circuit interrupts the emergency stop loop until the disconnection loop time is up.

Abstract: An electronic device with short frame time length is provided. The electronic device includes a substrate, a plurality of first signal lines, a plurality of second signal lines, and two first integrated circuits. The plurality of first signal lines are disposed on the substrate. The plurality of first signal lines are divided into a first group of signal lines and a second group of signal lines. The plurality of second signal lines are disposed on the substrate. The plurality of second signal lines are disposed alternately with the plurality of first signal lines. The two first integrated circuits are bonded on the substrate. Each of the two first integrated circuits are electrically connected to the first group of signal lines and the second group of signal lines. The first group of signal lines and the second group of signal lines are disposed alternately in columns.

Abstract: An internally dismantled anti-typhoon soundproof horizontal sliding window, which is fastened to an outer frame body and is provided with at least one outer sliding window and an inner sliding window; it is characterized in that: the outer side of the outer frame body is provided with at least one outer fixing column, an elastically movable top plate is provided on the inside and outside of the outer fixed column; when the two windows are closed, a central control lock can be used to drive the top plate to move through the inner columns of the outer and inner windows inwardly, the top plate squeezes the two inner column clamps tightly; the outer column of the outer frame body is provided with a hook, which can be used for the outer sliding window and the outer column of the inner sliding window; a snap cover that seals the grooves of the outer frame; thus, the window structure can be tightly closed in an all-round way, so as to meet the requirements of windproof, rainproof and sound insulation of the strong t

Abstract: Systems and methods are provided for a self-biasing electro-static discharge (ESD) power clamp. The ESD power clamp comprises an ESD detection circuit coupled to a positive supply voltage node and a ground voltage node. The ESD detection circuit includes a first node having a first voltage level during a standby mode and a second voltage level during an ESD mode. The ESD power clamp further comprises a discharge circuit coupled to the ESD detection circuit that includes a plurality of discharge elements a self-biasing node having a third voltage level during the standby mode. The third voltage level provides a voltage drop across at least one of the discharge elements that is less than the first voltage level. The discharge circuit provides a high-impedance path during the standby mode and a low-impedance path during the ESD mode.

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.

Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic structure and a wall structure surrounding the electronic structure are disposed on a carrier structure, a heat conducting layer is formed on the electronic structure, and the wall structure and the heat conducting layer are covered by a heat dissipation element. Therefore, a thermal stress can be effectively dispersed by the arrangement of the wall structure, such that a warpage of the electronic structure and a heat dissipation body can be effectively controlled.

Abstract: The disclosure provides an electronic apparatus and a manufacturing method thereof. The electronic apparatus includes a first insulating layer, a first metal layer, a second metal layer, a PN junction assembly, and a transistor circuit. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer is formed above the second surface. The second metal layer is formed on the second surface. The PN junction assembly is disposed on the first surface and electrically connected with the first metal layer and the second metal layer. The PN junction assembly includes a variable capacitor. The transistor circuit is electrically connecting with the second metal layer.

Abstract: A diode structure includes a silicon remaining layer, a first p-type doping region disposed on the silicon remaining layer and a first n-type doping region disposed on the silicon remaining layer. A first channel region is disposed on the silicon remaining layer and between the p-type doping region and the n-type doping region, wherein the first channel region, the first p-type doping region, and the first n-type doping region are disposed along a first direction.

Abstract: A method forming a semiconductor package device includes: providing a substrate; forming a flip chip die on a first side on the substrate; and forming a molding compound on the first side of the substrate. The molding compound covers the flip chip die. The method further includes forming a heat sink on the molding compound; and forming a taping layer on a second side of the substrate, wherein the second side is opposite from the first side in a vertical direction. After forming the taping layer, the method further includes performing a pre-cut process and an etching process on the heat sink; and removing the taping layer.

Abstract: An electronic device is provided. The electronic device includes a substrate, a conductive layer, an insulating layer, and a modulating material. The conductive layer is disposed on the substrate and has a first opening penetrating through the conductive layer. The insulating layer is disposed on the conductive layer and includes a second opening penetrating through the insulating layer. The first opening of the conductive layer and the second opening of the insulating layer are at least partially overlapped. The modulating material is disposed on the insulating layer.

Abstract: A manufacturing method of an electronic device is provided. The manufacturing method of the electronic device includes following steps: providing a substrate; bonding at least one electronic component to the substrate, wherein the at least one electronic component is mainly driven by a reverse bias in an operating mode; applying a forward bias to the at least one electronic component, and determining whether the at least one electronic component is normal or failed; and transporting the substrate configured with the at least one electronic component determined to be normal to a next production site or repairing the at least one electronic component determined to be failed.

Abstract: An ESD clamp circuit has an ESD detection circuit connected between a first terminal and a second terminal, with a first output node and a second output node. The ESD detection circuit is configured to output respective first and second control signals at the first and second output nodes in response to an ESD event. A discharge circuit includes a p-type transistor having a source, a drain and a gate, with the gate connected to the first output node. An n-type transistor has a source, a drain and a gate, with the gate connected to the second output node. The drain is connected to the drain of the p-type transistor. The discharge circuit is configured to establish a first ESD discharge path from the first terminal, through the p-type transistor and the n-type transistor, to the second terminal, and to further establish a second ESD discharge path in parallel with the first ESD discharge path. The second ESD discharge path includes a parasitic silicon controlled rectifier (SCR).

Abstract: The disclosure provides an electronic apparatus. The electronic apparatus includes an insulator, a driving unit, an electronic unit, and a circuit unit. The driving unit is overlapped with the insulator. The electronic unit is overlapped with the insulator. The circuit unit is electrically connected to the driving unit. The driving unit receives a signal from the circuit unit and drives the electronic unit.

Abstract: Disclosed is an electronic device including a tunable element, a first power supply circuit, and a second power supply circuit. The first power supply circuit and the second power supply circuit are electrically connected to the tunable element. The first power supply circuit drives the tunable element during a first time period. The second power supply circuit drives the tunable element during a second time period.

Abstract: An antenna device is provided, which includes a first substrate, and a second substrate facing and spaced with the first substrate in a distance. At least one working element disposed between the first substrate and the second substrate, wherein the at least one working element is filled with a modulation material. At least one buffer element is connected with the at least one working element for adjusting the amount of the modulation material in the at least one working element.

Abstract: An antifuse-type non-volatile memory cell includes a select transistor, a following transistor and a capacitor. The first drain/source terminal of the select transistor is connected with a bit line. The gate terminal of the select transistor is connected with a word line. A first drain/source terminal of the following transistor is connected with a second drain/source terminal of the select transistor. A gate terminal of the following transistor is connected with a following line. A second drain/source terminal of the following transistor is connected with a first terminal of the capacitor. A second terminal of the capacitor is connected with an antifuse control line.