Abstract: A semiconductor device includes a device wafer having a first side and a second side. The first and second sides are opposite to each other. The semiconductor device includes a plurality of first interconnect structures disposed on the first side of the device wafer. The semiconductor device includes a plurality of second interconnect structures disposed on the second side of the device wafer. The plurality of second interconnect structures comprise a first power rail and a second power rail. The semiconductor device includes a carrier wafer disposed over the plurality of first interconnect structures. The semiconductor device includes an electrostatic discharge (ESD) protection circuit formed over a side of the carrier wafer. The ESD protection circuit is operatively coupled to the first and second power rails.

Abstract: An electronic device includes a substrate, a metal layer, a first dielectric layer, a first conductive circuit, and a driving chip. The metal layer is provided on the substrate and has a first opening. The first dielectric layer is provided on the metal layer. The first conductive circuit is provided on the first dielectric layer. The driving chip is provided on the first dielectric layer and electrically connected to the first conductive circuit. The first opening is adjacent to the driving chip. The first conductive circuit overlaps the first opening. The electronic device of the disclosure may reduce the risk of a short circuit between the conductive circuit and the metal layer below when performing patching, function analysis, or failure analysis.

Abstract: A layout routing method includes determining a routing pattern according to a swapping rule, a via pattern, area constraints and pin locations; optimizing swapping in differential pairs according to the routing pattern; extracting features of each routing net to obtain extracted features; using an unsupervised algorithm to generate different routing groups according to the extracted features; and determining a routing order of the routing groups according to complex features of the routing groups.

Abstract: An apparatus is disclosed for robust transistor circuitry. In example implementations, an apparatus includes a current mirror and fault handler circuitry that is coupled to the current mirror. The current mirror includes a core transistor having a control terminal, a first transistor, and a second transistor. The first transistor has a control terminal that is coupled to the control terminal of the core transistor. The second transistor has a control terminal that is coupled to the control terminal of the core transistor. The fault handler circuitry is configured to select the first transistor or the second transistor to provide a mirrored current of the current mirror.

Abstract: An ESD protection device includes a PN diode formed in a semiconductor body. The PN diode has a first contact coupled to a metal structure on a front side of the semiconductor body and a second contact coupled to a metal structure on a back side of the semiconductor body. The metal coupled to the first contact is spaced apart from the metal coupled to the second contact by a thickness of the semiconductor body. This spacing greatly reduces the capacitance associated with the metal structures, which can substantially reduce the overall capacitance added to an I/O channel by the ESD protection device and thereby improve the performance of a high-speed circuit that uses the I/O channel.

Abstract: An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus comprises: an internal circuit formed in a first wafer; an array of electrostatic discharge (ESD) circuits formed in a second wafer, wherein the ESD circuits include a plurality of ESD protection devices each coupled to a corresponding switch and configured to protect the internal circuit from a transient ESD event; and a switch controller in the second wafer, wherein the switch controller is configured to control, based on a control signal from the first wafer, each of the plurality of ESD protection devices to be activated or deactivated by the corresponding switch, and wherein the first wafer is bonded to the second wafer.

Abstract: The disclosure provides an electronic apparatus and a manufacturing method thereof. The electronic apparatus includes a first insulating layer, a first metal layer, a second metal layer, and an electronic assembly. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer has an opening and is formed on the first surface. The second metal layer is formed on the second surface and a projection of the opening on the second surface is overlapped with a projection of the second metal layer on the second surface. The electronic assembly is electrically connected with the first metal layer and the second metal layer.

Abstract: An integrated circuit (IC) device includes an antenna effect protection device, and a to-be-protected device. A first source/drain of the antenna effect protection device is electrically coupled to a first conductor configured to carry a reference voltage. A second source/drain of the antenna effect protection device is electrically coupled by a second conductor to a gate of the to-be-protected device. The antenna effect protection device is a bulk-less device.

Abstract: The present disclosure provides a master-slave robot arm control system and method. The control method includes steps of: (a) providing a master and a slave robot arms; (b) executing a robot arm demonstration task, wherein the step (b) includes steps of: (b1) utilizing the slave robot arm to output a force feedback; (b2) generating an action command by operating the master robot arm; (b3) calculating and generating a movement command; (b4) controlling the slave robot arm to move and to generate a movement trajectory and the force feedback correspondingly; (c) repeating the step (b) to collect a plurality of movement trajectories of the slave robot arm; (d) utilizing a statistic module to analyze the plurality of movement trajectories; (e) generating an optimized trajectory of the slave robot arm; and (f) controlling the slave robot arm to execute a robot arm task.

Abstract: Provided herein are novel compositions enriched in gdT cells with high therapeutic potential. Methods to produce such compositions and methods of uses thereof in adoptive immunotherapies are also provided.

Abstract: The disclosure provides an electromagnetic wave adjustment apparatus includes a control circuit, a transistor circuit die and an electronic assembly. The transistor circuit die receives a control signal from the control circuit and drives the electronic assembly.

Abstract: A light detection method for a light detection device is provided. The light detection device includes multiple scan lines and multiple light sensing elements. Each of the light sensing elements is coupled to a corresponding one of the scan lines. The light detection method includes: in a detection mode, sequentially scanning a first scan line to a (N+1)th scan line among the scan lines, wherein a Nth scan line is not adjacent to at least one of a (N?1)th scan line and the (N+1)th scan line; reading signals of the light sensing elements coupled to the first scan line to the (N+1)th scan line; determining whether the signals meet an exposure standard; and controlling the light detection device to enter a value reading mode when the signals meet the exposure standard.

Abstract: An ESD clamp circuit has an ESD detection circuit connected between a first terminal and a second terminal, with a first output node and a second output node. The ESD detection circuit is configured to output respective first and second control signals at the first and second output nodes in response to an ESD event. A discharge circuit includes a p-type transistor having a source, a drain and a gate, with the gate connected to the first output node. An n-type transistor has a source, a drain and a gate, with the gate connected to the second output node. The drain is connected to the drain of the p-type transistor. The discharge circuit is configured to establish a first ESD discharge path from the first terminal, through the p-type transistor and the n-type transistor, to the second terminal, and to further establish a second ESD discharge path in parallel with the first ESD discharge path. The second ESD discharge path includes a parasitic silicon controlled rectifier (SCR).

Abstract: The present disclosure describes systems and techniques directed to optical image stabilization movement to create a super-resolution image of a scene. The systems and techniques include a user device (102) introducing (502), through an optical image stabilization system (114), movement to one or more components of a camera system (112) of the user device (102). The user device (102) then captures (504) respective and multiple frames (306) of an image of a scene, where the respective and multiple frames (306) of the image of the scene have respective, sub-pixel offsets of the image of the scene across the multiple frames (306) as a result of the introduced movement to the one or more components of the camera system (112). The user device (102) performs (506), based on the respective, sub-pixel offsets of the image of the scene across the respective, multiple frames (306), super-resolution computations and creates (508) the super-resolution image of the scene based on the super-resolution computations.

Abstract: An antenna element comprises one or more directors, a resonator, and a three dimensional ground assembly. Parts of the antenna element are arranged on three metal layers. A top layer has an unconnected metal bar which forms a beam director, a resonator and a top part of the ground assembly. The resonator is an integral piece substantially in the form of a loop connected to a feed line and a feed line terminal ending. The feed line terminal ending serves as the ground plane for the feed line as well as providing impedance matching from the external transceiver circuit to the resonator. The ground assembly includes a top layer ground connected to a plurality of metallized half cylindrical hole channels (or metallized via holes) which connect to a ground terminal in a bottom layer.

Abstract: A light-emitting device includes a semiconductor stack, an insulating reflective structure having an opening, and an electrode located on the insulating reflective structure and filled in the opening to electrically connect to the semiconductor stack. The semiconductor stack having includes a main surface, and a side surface inclined to the main surface. The light-emitting device has a dominant wavelength and a peak wavelength. The insulating reflective structure includes: a first part located on the main surface and having a first thickness; and a second part located on the side surface and having a second thickness different from the first thickness. The second part of the insulating reflective structure has a reflectivity of more than 90% for the dominant wavelength or the peak wavelength within an incident angle of 0° to 30°.