Patents by Inventor Yi-Jen Lai

Yi-Jen Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145908
    Abstract: An electronic package and a manufacturing method thereof are provided, in which an electronic element is disposed on a carrier structure, and an antenna structure is stacked on the carrier structure via conductors, where at least one through hole is formed on and penetrating through the antenna structure, and an insulating support body is formed between the carrier structure and the antenna structure, so that the insulating support body is correspondingly formed at the through hole and/or an edge of the antenna structure, and the through hole is free from being filled up by the insulating support body, such that the through hole has an air medium. The design of the through hole allows the characteristic of the dielectric constant of air being 1 to be utilized so as to reduce the signal loss and the signal offset, thereby facilitating the signal transmission of the antenna body.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Yi-Chun LAI, Hsuan-Jen WANG, Rung-Jeng LIN
  • Patent number: 11923353
    Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jen Lai, Chung-Yi Lin, Hsi-Kuei Cheng, Chen-Shien Chen, Kuo-Chio Liu
  • Publication number: 20230369152
    Abstract: A package includes a die, first conductive structures, second conductive structures, and an encapsulant. The die has a rear surface. The first conductive structures and the second conductive structures surround the die. The first conductive structures include cylindrical columns and the second conductive structures include elliptical columns. At least one of the second conductive structures is closer to the die than the first conductive structures. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 16, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
  • Patent number: 11756849
    Abstract: A package includes a die, first conductive structures, second conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The first conductive structures and the second conductive structures surround the die. A shape of the first conductive structures is different a shape of the second conductive structures. The second conductive structures include elliptical columns having straight sidewalls. A distance between the first conductive structure that is closest to the die and the die is greater than a distance between the second conductive structure that is closest to the die and the die. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures. The redistribution structure is over the die and the encapsulant. The redistribution structure is electrically connected to the die, the first conductive structures, and the second conductive structures.
    Type: Grant
    Filed: June 8, 2022
    Date of Patent: September 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
  • Publication number: 20230193436
    Abstract: Provided is a stainless steel powder composition, which comprises Cr, Cu, Mn, Mo, Ni and Fe; wherein, based on a total weight of the stainless steel powder composition, a content of Cr is 20 wt% to 24 wt%, and a content of Cu is more than 0 wt% and less than or equal to 0.5 wt%, a content of Mn is more than 0 wt% and less than or equal to 2 wt%, a content of Mo is 2.25 wt% to 3 wt% and a content of Ni is 10 wt% to 15 wt%. When applying the stainless steel powder composition of the present invention to laser additive manufacturing (LAM), the produced stainless steel workpiece has enhanced tensile strength, thereby expanding the follow-up applications and increasing the commercial value.
    Type: Application
    Filed: December 19, 2022
    Publication date: June 22, 2023
    Inventors: CHIEN-HUNG YEH, CHENG-CHIN WANG, CHANG-FU WANG, YI-JEN LAI, HONG-YI CHEN
  • Publication number: 20220399325
    Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.
    Type: Application
    Filed: July 27, 2022
    Publication date: December 15, 2022
    Inventors: Yi-Jen Lai, Chung-Yi Lin, Hsi-Kuei Cheng, Chen-Shien Chen, Kuo-Chio Liu
  • Patent number: 11488891
    Abstract: A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate. The method includes depositing a first-side UBM layer on a first surface of the semiconductor substrate. The method includes forming a plurality of first-side metal bumps on the first surface of the semiconductor substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the semiconductor substrate. The method includes forming a plurality of second-side metal bumps on the second surface of the semiconductor substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: You-Hua Chou, Yi-Jen Lai, Chun-Jen Chen, Perre Kao
  • Publication number: 20220301964
    Abstract: A package includes a die, first conductive structures, second conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The first conductive structures and the second conductive structures surround the die. A shape of the first conductive structures is different a shape of the second conductive structures. The second conductive structures include elliptical columns having straight sidewalls. A distance between the first conductive structure that is closest to the die and the die is greater than a distance between the second conductive structure that is closest to the die and the die. The encapsulant encapsulates the die, the first conductive structures, and the second conductive structures. The redistribution structure is over the die and the encapsulant. The redistribution structure is electrically connected to the die, the first conductive structures, and the second conductive structures.
    Type: Application
    Filed: June 8, 2022
    Publication date: September 22, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
  • Patent number: 11437361
    Abstract: A method includes forming a release film over a carrier, forming a polymer buffer layer over the release film, forming a metal post on the polymer buffer layer, encapsulating the metal post in an encapsulating material, performing a planarization on the encapsulating material to expose the metal post, forming a redistribution structure over the encapsulating material and the metal post, and decomposing a first portion of the release film. A second portion of the release film remains after the decomposing. An opening is formed in the polymer buffer layer to expose the metal post.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Jen Lai, Lin Chung-Yi, Hsi-Kuei Cheng, Chen-Shien Chen, Kuo-Chio Liu
  • Patent number: 11404341
    Abstract: A package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The conductive structures include elliptical columns. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is over the active surface of the die and the encapsulant. The redistribution structure is electrically connected to the die and the conductive structures.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: August 2, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
  • Publication number: 20220173083
    Abstract: A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.
    Type: Application
    Filed: February 16, 2022
    Publication date: June 2, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dong-Han Shen, Chen-Shien Chen, Kuo-Chio Liu, Hsi-Kuei Cheng, Yi-Jen Lai
  • Patent number: 11257797
    Abstract: A package on package structure includes a first package, a plurality of conductive bumps, a second package and an underfill. The conductive bumps are disposed on a second surface of the first package and electrically connected to the first package. The second package is disposed on the second surface of the first package through the conductive bumps, and includes a semiconductor device and an encapsulating material encapsulating the semiconductor device. A shortest distance from an upper surface of the encapsulating material to an upper surface of the semiconductor device is greater than or substantially equal to twice a thickness of the semiconductor device. The underfill is filled between the first package and the second package.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dong-Han Shen, Chen-Shien Chen, Kuo-Chio Liu, Hsi-Kuei Cheng, Yi-Jen Lai
  • Patent number: 11217548
    Abstract: A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Guo Lee, Yung-Sheng Liu, Yi-Chen Liu, Yi-Jen Lai, Chun-Jen Chen, Hsi-Kuei Cheng
  • Patent number: 11201142
    Abstract: A semiconductor package includes a die, an insulation layer, a plurality of first electrical conductive vias, a plurality of second electrical conductive vias, a plurality of thermal conductive vias and a connecting pattern. The die includes a plurality of first pads and a plurality of second pads. The insulation layer is disposed on the die and includes a plurality of openings exposing the first pads and the second pads. The first electrical conductive vias and the second electrical conductive vias are disposed in the openings and contact the first pads and the second pads respectively. The thermal conductive vias are disposed on the insulation layer. The connecting pattern is disposed on the insulation layer and connects the first electrical conductive vias and the thermal conductive vias. The thermal conductive vias are connected to the first pads through the connecting pattern and the first electrical conductive vias.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: December 14, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hsien Huang, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Hua-Wei Tseng, Ming-Chih Yew, Yi-Jen Lai, Ming-Shih Yeh
  • Patent number: 11145613
    Abstract: Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a resist layer having an opening over the metal layer. The method for forming a semiconductor structure further includes forming a conductive pillar and a solder layer over the conductive pillar in the opening of the resist layer and removing the resist layer. The method for forming a semiconductor structure further includes removing a portion of the conductive pillar so that the conductive pillar has an angled sidewall.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Li-Guo Lee, Yung-Sheng Liu, Yi-Chen Liu, Yi-Jen Lai, Chun-Jen Chen, Hsi-Kuei Cheng
  • Patent number: 10867976
    Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
  • Publication number: 20200258814
    Abstract: A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate. The method includes depositing a first-side UBM layer on a first surface of the semiconductor substrate. The method includes forming a plurality of first-side metal bumps on the first surface of the semiconductor substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the semiconductor substrate. The method includes forming a plurality of second-side metal bumps on the second surface of the semiconductor substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.
    Type: Application
    Filed: April 30, 2020
    Publication date: August 13, 2020
    Inventors: You-Hua CHOU, Yi-Jen LAI, Chun-Jen CHEN, Perre KAO
  • Publication number: 20200194326
    Abstract: A package includes a die, a plurality of conductive structures, an encapsulant, and a redistribution structure. The die has an active surface and a rear surface opposite to the active surface. The conductive structures surround the die. The conductive structures include elliptical columns. The encapsulant encapsulates the die and the conductive structures. The redistribution structure is over the active surface of the die and the encapsulant. The redistribution structure is electrically connected to the die and the conductive structures.
    Type: Application
    Filed: February 24, 2020
    Publication date: June 18, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Huan Chiu, Chun-Jen Chen, Chen-Shien Chen, Kuo-Chio Liu, Kuo-Hui Chang, Chung-Yi Lin, Hsi-Kuei Cheng, Yi-Jen Lai
  • Patent number: 10651111
    Abstract: A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate includes depositing a first-side UBM layer on a first surface of the substrate, and forming a plurality of first-side metal bumps on the first surface of the substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the substrate, and the first surface and the second surface are opposite of each other. The method includes forming a plurality of second-side metal bumps on the second surface of the substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: May 12, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: You-Hua Chou, Yi-Jen Lai, Chun-Jen Chen, Perre Kao
  • Publication number: 20200118984
    Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.
    Type: Application
    Filed: December 11, 2019
    Publication date: April 16, 2020
    Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen