Patents by Inventor Yi-Jen Lai
Yi-Jen Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10163843Abstract: A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.Type: GrantFiled: October 27, 2017Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Guo Lee, Yung-Sheng Liu, Yi-Chen Liu, Yi-Jen Lai, Chun-Jen Chen, Hsi-Kuei Cheng
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Patent number: 10090267Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor structure further includes a modified conductive pillar having a top portion and a bottom portion formed over the metal pad and a solder layer formed over the modified conductive pillar. In addition, the top portion of the modified conductive pillar has a first sidewall in a first direction and a bottom portion of the modified conductive pillar has a second sidewall in a second direction different from the first direction.Type: GrantFiled: March 13, 2014Date of Patent: October 2, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Li-Guo Lee, Yung-Sheng Liu, Yi-Chen Liu, Yi-Jen Lai, Chun-Jen Chen, Hsi-Kuei Cheng
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Publication number: 20180166361Abstract: A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate includes depositing a first-side UBM layer on a first surface of the substrate, and forming a plurality of first-side metal bumps on the first surface of the substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the substrate, and the first surface and the second surface are opposite of each other. The method includes forming a plurality of second-side metal bumps on the second surface of the substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.Type: ApplicationFiled: February 6, 2018Publication date: June 14, 2018Inventors: You-Hua CHOU, Yi-Jen LAI, Chun-Jen CHEN, Perre KAO
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Patent number: 9997482Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor structure further includes a solder stud formed over the metal pad, and the solder stud has a flat top surface parallel to a top surface of the first substrate.Type: GrantFiled: March 13, 2014Date of Patent: June 12, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Guo Lee, Yi-Chen Liu, Yung-Sheng Liu, Yi-Jen Lai, Chun-Jen Chen, Hsi-Kuei Cheng
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Publication number: 20180151512Abstract: A semiconductor device includes: a first dielectric layer having a first surface; a molding compound disposed on the first surface of the first dielectric layer; a second dielectric layer having a first surface disposed on the molding compound; a via disposed in the molding compound; and a first conductive bump disposed on the via and surrounded by the second dielectric layer; wherein the first dielectric layer and the second dielectric layer are composed of the same material. The filling material has a thickness between the second dielectric layer and the semiconductor die, and the diameter of the hole is inversely proportional to the thickness of the filling material.Type: ApplicationFiled: April 12, 2017Publication date: May 31, 2018Inventors: SHIN-PUU JENG, TZU-JUI FANG, HSI-KUEI CHENG, CHIH-KANG HAN, YI-JEN LAI, HSIEN-WEN LIU, YI-JOU LIN
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Publication number: 20180076184Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.Type: ApplicationFiled: August 4, 2017Publication date: March 15, 2018Inventors: Chen-Shien Chen, Hsiu-Jen Lin, Ming-Chih Yew, Ming-Da Cheng, Yi-Jen Lai, Yu-Tse Su, Sey-Ping Sun, Yang-Che Chen
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Publication number: 20180068967Abstract: A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.Type: ApplicationFiled: October 27, 2017Publication date: March 8, 2018Inventors: Li-Guo Lee, Yung-Sheng Liu, Yi-Chen Liu, Yi-Jen Lai, Chun-Jen Chen, Hsi-Kuei Cheng
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Patent number: 9899296Abstract: A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate includes depositing a first-side UBM layer on a first surface of the substrate, and forming a plurality of first-side metal bumps on the first surface of the substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the substrate, and the first surface and the second surface are opposite of each other. The method includes forming a plurality of second-side metal bumps on the second surface of the substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.Type: GrantFiled: January 9, 2015Date of Patent: February 20, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: You-Hua Chou, Yi-Jen Lai, Chun-Jen Chen, Perre Kao
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Publication number: 20180033756Abstract: Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a metal pad over a first substrate and forming a polymer layer over the metal pad. The method for forming a semiconductor structure further includes forming a seed layer over the metal pad and extending over the polymer layer and forming a conductive pillar over the seed layer. The method for forming a semiconductor structure further includes wet etching the seed layer using an etchant comprising H2O2. In addition, the step of wet etching the seed layer is configured to form an extending portion having a slope sidewall.Type: ApplicationFiled: October 5, 2017Publication date: February 1, 2018Inventors: Li-Guo LEE, Yi-Chen LIU, Yung-Sheng LIU, Yi-Jen LAI, Chun-Jen CHEN, Hsi-Kuei CHENG
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Patent number: 9806046Abstract: A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.Type: GrantFiled: March 13, 2014Date of Patent: October 31, 2017Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Li-Guo Lee, Yung-Sheng Liu, Yi-Chen Liu, Yi-Jen Lai, Chun-Jen Chen, Hsi-Kuei Cheng
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Patent number: 9779969Abstract: A package structure and a manufacturing method are provided. The package structure includes a semiconductor substrate and a first conductive feature over the semiconductor substrate. The package structure also includes a substrate and a second conductive feature over the substrate. The second conductive feature is bonded with the first conductive feature through a bonding structure. The package structure further includes a protection material surrounding the bonding structure, and the protection material is in direct contact with a side surface of the first conductive feature.Type: GrantFiled: March 13, 2014Date of Patent: October 3, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Li-Guo Lee, Yung-Sheng Liu, Yi-Chen Liu, Yi-Jen Lai, Chun-Jen Chen, Hsi-Kuei Cheng
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Patent number: 9735123Abstract: A semiconductor device structure and a manufacturing method are provided. The method includes forming a conductive pillar over a semiconductor substrate. The method also includes forming a solder layer over the conductive pillar. The method further includes forming a water-soluble flux over the solder layer. In addition, the method includes reflowing the solder layer to form a solder bump over the conductive pillar and form a sidewall protection layer over a sidewall of the conductive pillar during the solder layer is reflowed.Type: GrantFiled: March 13, 2014Date of Patent: August 15, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Guo Lee, Yi-Chen Liu, Yung-Sheng Liu, Yi-Jen Lai, Chun-Jen Chen, Hsi-Kuei Cheng
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Patent number: 9594096Abstract: In accordance with an embodiment, a probe card comprises a contact pad interface comprising front side contacts and back side contacts electrically coupled together. The front side contacts are arranged to simultaneously electrically couple respective bumps of a plurality of dies on a wafer, and the back side contacts are arranged to electrically couple respective contacts of a testing structure.Type: GrantFiled: August 16, 2013Date of Patent: March 14, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: You-Hua Chou, Yi-Jen Lai
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Patent number: 9190347Abstract: A semiconductor device utilizing die edge contacts is provided. An integrated circuit die has a post-passivation layer with a trench filled with a conductive material extending from a contact to a die edge, thereby forming a die edge contact. Optionally, a through substrate via may be positioned along the die edge such that the conductive material in the trench is electrically coupled to the through-substrate via, thereby forming a larger die edge contact. The integrated circuit die may be placed in a multi-die package wherein the multi-die package includes walls having a major surface perpendicular to a major surface of the integrated circuit die. The die edge contacts are electrically coupled to contacts on the walls of the multi-die package. The multi-die package may include edge contacts for connecting to another substrate, such as a printed circuit board, a packaging substrate, a high-density interconnect, or the like.Type: GrantFiled: August 14, 2013Date of Patent: November 17, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Jen Lai, You-Hua Chou, Hon-Lin Huang, Huai-Tei Yang
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Publication number: 20150262951Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor structure further includes a modified conductive pillar having a top portion and a bottom portion formed over the metal pad and a solder layer formed over the modified conductive pillar. In addition, the top portion of the modified conductive pillar has a first sidewall in a first direction and a bottom portion of the modified conductive pillar has a second sidewall in a second direction different from the first direction.Type: ApplicationFiled: March 13, 2014Publication date: September 17, 2015Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Li-Guo LEE, Yung-Sheng LIU, Yi-Chen LIU, Yi-Jen LAI, Chun-Jen CHEN, Hsi-Kuei CHENG
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Publication number: 20150262955Abstract: A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.Type: ApplicationFiled: March 13, 2014Publication date: September 17, 2015Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Li-Guo LEE, Yung-Sheng LIU, Yi-Chen LIU, Yi-Jen LAI, Chun-Jen CHEN, Hsi-Kuei CHENG
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Publication number: 20150262846Abstract: A package structure and a manufacturing method are provided. The package structure includes a semiconductor substrate and a first conductive feature over the semiconductor substrate. The package structure also includes a substrate and a second conductive feature over the substrate. The second conductive feature is bonded with the first conductive feature through a bonding structure. The package structure further includes a protection material surrounding the bonding structure, and the protection material is in direct contact with a side surface of the first conductive feature.Type: ApplicationFiled: March 13, 2014Publication date: September 17, 2015Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Li-Guo LEE, Yung-Sheng LIU, Yi-Chen LIU, Yi-Jen LAI, Chun-Jen CHEN, Hsi-Kuei CHENG
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Publication number: 20150262953Abstract: A semiconductor device structure and a manufacturing method are provided. The method includes forming a conductive pillar over a semiconductor substrate. The method also includes forming a solder layer over the conductive pillar. The method further includes forming a water-soluble flux over the solder layer. In addition, the method includes reflowing the solder layer to form a solder bump over the conductive pillar and form a sidewall protection layer over a sidewall of the conductive pillar during the solder layer is reflowed.Type: ApplicationFiled: March 13, 2014Publication date: September 17, 2015Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Li-Guo LEE, Yi-Chen LIU, Yung-Sheng LIU, Yi-Jen LAI, Chun-Jen CHEN, Hsi-Kuei CHENG
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Publication number: 20150262952Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor structure further includes a seed layer formed over the metal pad and a conductive pillar formed over the seed layer. In addition, the seed layer has a sidewall and a bottom surface, and an angle between the sidewall and the bottom surface of the seed layer is in a range from about 20° to about 90°.Type: ApplicationFiled: March 13, 2014Publication date: September 17, 2015Applicant: Taiwan Semiconductor Manufacturing Co., LtdInventors: Li-Guo LEE, Yi-Chen LIU, Yung-Sheng LIU, Yi-Jen LAI, Chun-Jen CHEN, Hsi-Kuei CHENG
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Publication number: 20150262954Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate and a metal pad formed over the first substrate. The semiconductor structure further includes a solder stud formed over the metal pad, and the solder stud has a flat top surface parallel to a top surface of the first substrate.Type: ApplicationFiled: March 13, 2014Publication date: September 17, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Li-Guo LEE, Yi-Chen LIU, Yung-Sheng LIU, Yi-Jen LAI, Chun-Jen CHEN, Hsi-Kuei CHENG